Spartan 3A startup

[63077]

I have a Spartan 3a (xa3s200) and a Platform flash (xcf02), they both seem to program and verify, they are tied in serial with JTAG...

can I use the same bit file that uses cclk or do I have to use JTAG clk for it to start.... I see cclk running and DONE never goes HI...

I have tested the code in a xa3s400 part on a demo board and it all works OK... that board uses BPI....

The board is jumpered for Master Serial Mode '000'

[gszakacs]

Since you say they "both" program and verify, I assume you can use Impact to program the

FPGA or the flash.  When you say DONE never goes high, I assume you mean after power-cycling

the board the FPGA does not load from flash.

The proper bitgen settings for Master Serial mode is to use CCLK for start-up.  When you program

the FPGA directly using Impact it will automatically change to JTAG clock for start-up,

but this doesn't change the bitstream you program to the the flash.  For the XCF02S you would

normally generate a .mcs file from the .bit file which was generated using CCLK as the startup

clock.

If you change the Bitgen settings to use JTAG clock for startup and make a .mcs file from that

.bit file, your FPGA will not start up.

There are other reasons why CCLK could run on without ever having DONE go high.  This could happen

if the file you programmed into the XCF02S has the bits swapped for example.

HTH,

Gabor

[63077]

Thanks for the reply...

Yes I am using Impact with the usb 2 pod... I am setting the cclk, also have set the device signature and with a power cycle I reads it correctly out of the FPGA...

If I pulse prog_b it doesn't make any improvement... I was worried about the pwr supply sequencing so I add a scope photo of that on power-up.... I can see

the data coming out of the Platform Flash... and the speed change... I think am going to slow the clock down, it is now set for 10Mhz.. I am using the serial platform flash, does that

have a swapping issue with Impact..

Regards,

Cliff 

[gszakacs]

If you set the device to XCF02S in Impact it should prepare the .mcs file properly.  I have

only seen problems with bit order when preparing generic .hex files in impact.  10 MHz

does not sound too fast for this part unless you have a long chain.  You may want to check the CCLK

signal integrity at the XCF02S to make sure you're not getting ringing that could be

detected as extra clock pulses.  Generally the XCF02S will not be as sensitive to such

problems as the FPGA, so Master Serial mode tends to just work.  There are definitely

issues with poor CCLK signal quality in Slave modes where the FPGA is receiving

the clock and has much more sensitivity to false clocks due to ringing or slow

rise and fall times.  The Spartan 3 family configuration user' guide is your best source

of information on how to guarantee proper start-up.

Regards,

Gabor

[63077 · Accepted solution]

Hi Gabor

Thanks for the help... I have fixed the problem, I had a buffer connected to the DONE signal to drive an LED and a RFI filtered signal to a connector, the pin on the connector was named DONE as was the signal on the local DONE net, hence with the postitive hysterisis of the buffer the DONE signal stayed low... I got directed here by using the Read Device Status in Impact and realized the DCM had locked... Therefore the FPGA must have booted... All is well

Thanks

Cliff

[adw]

i m doing project on spartan 3A "REAL TIME OBJECT DETECTION AND TRACKING" and i don't know any thing about SPARTAN 3A.can u plz send m code of how to get real time video n output to DVI out?

i hv seen demos but they r not helpfull plz send m verilog code of video in n out.

i hv biult a simulink model but HDl-coder can't convert model to verilg n gives error "matrices r not supported in this release"