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Historian
Historian
3,932 Views
Registered: ‎02-25-2008

Spartan 3AN left-half and right-half clocks and quadrants

I've been trying to get pins selected for an XC3S200AN design for the last day, and the tools keep yelling at me.

 

I have five incoming LVDS clocks. One is an FPGA global clock, and the other four are from four ADCs, with source-synchronous data from each. A DCM is not necessary.

 

My first thought was that there are enough global clocks on the top and bottom to support this; three on the bottom (GCLK0/1, GCLK2/3, GCLK14/15, GCLK4/5, GCLK6/7). But the tools weren't happy and for some reason couldn't route the three clocks on the bottom to their respective BUFGs. No amount of locating clock buffers, wiring BUFGMUXes or any of that would stop it from complaining about using a non-direct route from the clock pins through the IBUFGDS to the BUFG would satisfy the tools (ISE 13.3, but I've fought this kind of battle since at least ISE 10, because the tools are too fscking stupid to just select the nearest direct BUFG, which is documented in the user guide).

 

So I decided to put the four ADC clocks on left-hand and right-hand clock inputs. One clock is on the pair for LHCLK2, another is on the LHCLK4 pair, the third is on the RHCLK0 pair, and the fourth is on the RHCLK6 pair. I've set location constraints on the relevant BUFGs according to Table 2-7 in the user guide UG331. The pins that are inputs clocked out by each of these four clocks (and hence into the FPGA on them) are placed in the proper banks on the correct side of the chip.

 

The placer throws a warning: 

WARNING:Place:1263 - Initial clock placement failed. Yadda yadda yadda.

 

Then it throws an error:

ERROR:Place:1138: Automatic clock placement failed. Yadda yadda yadda. Followed by a list of "Competing Global/Side clock buffers."

 

I used PlanAhead and tried to constrain the stuff clocked by those LH/RH clocks into quadrants, and still get the above complaints.

 

So, what's not clear to me is: even though the Left-Hand and Right-Hand clocks are called Left-Hand and Right-Hand, are they really Quadrant clocks or are they actually half-the-chip clocks? The User Guide is remarkable obtuse. 

 

Or is it best to simply avoid the LH and RH clocks entirely, and add the directive to stop the error about using the wrong routing to a BUFG that results when I try to put three LVDS clocks on the top or bottom?

----------------------------Yes, I do this for a living.
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4 Replies
Teacher eteam00
Teacher
3,931 Views
Registered: ‎07-21-2009

Re: Spartan 3AN left-half and right-half clocks and quadrants

Quick question for you...  Will the FPGA editor allow you to 'do the right thing' (as in BUFG placement and hookup) ?

 

-- Bob Elkind

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Historian
Historian
3,927 Views
Registered: ‎02-25-2008

Re: Spartan 3AN left-half and right-half clocks and quadrants


@eteam00 wrote:

Quick question for you...  Will the FPGA editor allow you to 'do the right thing' (as in BUFG placement and hookup) ?

 

-- Bob Elkind


I haven't tried the FPGA editor; PlanAhead happily accepts my pin placement and BUFG location.

 

It turns out that by putting the "CLOCK_DEDICATED_ROUTE = FALSE" constraint on the offending clock input allows the tools to move forward, and it doesn't seem like there's any particular penalty.

 

The consensus here is that the error is bogus and the tools should have been fixed ages ago. But Xilinx isn't going to fix this problem, so there it is.

----------------------------Yes, I do this for a living.
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Instructor
Instructor
3,918 Views
Registered: ‎08-14-2007

Re: Spartan 3AN left-half and right-half clocks and quadrants


@bassman59 wrote:

@eteam00 wrote:

Quick question for you...  Will the FPGA editor allow you to 'do the right thing' (as in BUFG placement and hookup) ?

 

-- Bob Elkind


I haven't tried the FPGA editor; PlanAhead happily accepts my pin placement and BUFG location.

 

It turns out that by putting the "CLOCK_DEDICATED_ROUTE = FALSE" constraint on the offending clock input allows the tools to move forward, and it doesn't seem like there's any particular penalty.

 

The consensus here is that the error is bogus and the tools should have been fixed ages ago. But Xilinx isn't going to fix this problem, so there it is.


Just for clarity, are you saying the the net with the "CLOCK_DEDICATED_ROUTE = FALSE" constraint

is actually using an optimal route to the BUFG when Place&Route is all done?

 

-- Gabor

-- Gabor
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Historian
Historian
3,913 Views
Registered: ‎02-25-2008

Re: Spartan 3AN left-half and right-half clocks and quadrants


@gszakacs wrote:


Just for clarity, are you saying the the net with the "CLOCK_DEDICATED_ROUTE = FALSE" constraint

is actually using an optimal route to the BUFG when Place&Route is all done?

 

-- Gabor



Yes, as far as I can tell from the FPGA editor, it does. 

 

And it would still be nice to get the side clocks to work.

----------------------------Yes, I do this for a living.
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