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Contributor
Contributor
7,324 Views
Registered: ‎01-05-2010

Spartan 3AN

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Hello,

I am a beginner with FPGA and i am working wuth SPARTAN 3AN.

i was looking at the datasheet, and reading about the internal system flash.

i was wondering, is it true that by just configuring the pins correctly, you can make the FPGA load itself with its image at startup without any user interference? or is there any trick i am missing?

thank you

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Contributor
Contributor
9,425 Views
Registered: ‎01-05-2010

Re: Spartan 3AN

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Yes i understand that now.

Last night i succeeded in designing the SPI Master and simulated it perfectly using modelsim !

Thank you.

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Scholar austin
Scholar
7,321 Views
Registered: ‎02-27-2008

Re: Spartan 3AN

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b,

 

Yes.  That is the whole idea behind this device:  make it so the whole design can be loaded in a few milliseconds after power ON.

 

The flash is big enough to also put something else it there as well:  another deisgn image, or use it for storing software code for a soft processor.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Contributor
Contributor
7,316 Views
Registered: ‎01-05-2010

Re: Spartan 3AN

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Thank you.

it is amazing really.

i am just looking at the code for the SPI_ACCESS which should allow a read/write from the flash.

and i saw it reads on the positive edge of the clock, even though i understood from the documentation that it reads data on the negative edge of clock, perhaps i was wrong.

Currently i am trying to design a Compatible SPI Master, hope i can succeed.

Thanks again.

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Historian
Historian
7,305 Views
Registered: ‎02-25-2008

Re: Spartan 3AN

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bkazour wrote:

Thank you.

it is amazing really.

i am just looking at the code for the SPI_ACCESS which should allow a read/write from the flash.

and i saw it reads on the positive edge of the clock, even though i understood from the documentation that it reads data on the negative edge of clock, perhaps i was wrong.

Currently i am trying to design a Compatible SPI Master, hope i can succeed.

Thanks again.


It's common for SPI data to be asserted (driven out) on the falling edge of the clock and registered in (read) on the rising edge. If you look at page 11 of UG333 (v2.1) you will see Figure 1-2 which makes this clear.

It is VERY easy to write code for an SPI master that does this.

----------------------------Yes, I do this for a living.
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Contributor
Contributor
9,426 Views
Registered: ‎01-05-2010

Re: Spartan 3AN

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Yes i understand that now.

Last night i succeeded in designing the SPI Master and simulated it perfectly using modelsim !

Thank you.

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Newbie oceanboy
Newbie
7,047 Views
Registered: ‎04-25-2010

Re: Spartan 3AN

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Hello,I am a newer to FPGA ,and I also want to use SPI_ACCESS but I don't know how to write VHDL code to achieve that.Could you please send some certain code to me?Thank you very much.My email is qiuhuijieqifeng@126.com
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Adventurer
Adventurer
5,550 Views
Registered: ‎02-05-2014

Re: Spartan 3AN

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Hi 

 

      I wrote this verilog code for to access (read & write ) operation in spartan 3an(XC3S50AN) evaluation kit . i followed these procedures for access the FLASH byte address .but there wont have any result in that MISO_OUT  after i implement in to the device. i could not find whether its writing in to the chip or not  like.....! pls can u verify this simulation picture and coding wheter any wrong procedures i folloewd in this process . my motive is i should write and read the bytes like EEPROM flash memory .

 

        CSB LOW                                                        - rising edge of clk

        24 BIT ADDRESS for write                           - falling edge of clock ( MOSI_IN)

        24 BIT ADDRESS for READ                         -falling edge of clock ( MOSI_IN),

        READ BYTE                                                    - falling edge of MISO_OUT

        CSB    HIGH                                                    - falling edge of clock 

        

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