10-30-2009 04:23 PM - edited 10-30-2009 04:41 PM
I am designing a FPGA-based signal processing unit with ADCs and DACs (about 1MSPS sampling rate, max. 32MHz to 50 MHz SPI data clock rate). The system will be clocked by a 50MHz oscillator (internally increased to 150MHz by a DCM). The first prototype was designed as extension to the Spartan-3E Starter-Kit, now I am designing the complete system. Unfortunately I have to use the PQ208 package as we are not able to solder BGA-packages. The PCB only has two copper-layers (top/bottom) where the bottom layer will be mainly used as groundplane.
Now I have got some questions:
Thanks for any help in advance.
10-30-2009 09:06 PM
I imagine your end product is cost sensitive or else you wouldn't consider a 2-layer board,
however I believe you're asking for trouble with high-speed logic on two layers. If the
board must be 2 layers because it has a large area for other slow stuff, you might
consider a module for the Spartan. There are some examples on the Enterpoint
website, for example the Darnaw1 with a pin grid array footprint and all decoupling
If your board is relatively small, the cost to go to 4 layers may be less than you think
and in my opinion worth the difference. You REALLY want to have a solid ground
plane and the 4-layer would allow your bypass components to go on the back
of the board. In addition, using the other inner layer as a split plane for power
gives some additional high-speed decoupling you won't get with any amount of
capacitors on a two-layer construction.
10-30-2009 09:29 PM
My guess is that you can get away with 2 layers if your bottom layer is not too broken up, and your bypassing is good. But with only 2 layers it is hard to get a ground plane that's not like swiss cheese.
We did a 3E-500 PQ208 design using a 4 layer board, with a 0.1uF ceramic cap per power pin a couple of years ago and it worked well. Put caps close to the pins, use heavier traces for power. One big cap like at least 10uF low ESR somewhere on board for each voltage. Just basic good layout practice.
I found that the 1.2V core generated a fair amount of hash, so bypass that well and keep it away from your analog side. One thing I found really effective for decoupling is small ferrite beads. We used Steward MI1206K601R-10 which are 1206 case size.
We just did a design with a 3A-700 in FT256 BGA package - the BGAs are not that bad and there are many board houses now that will solder and xray them for you, even small quantities ... you can put on the rest of the parts yourself. The ball spacing is 1mm which gives you enough room to run a trace between.
09-04-2012 11:01 PM
can you or someone else explain how to select the beads to use for the FPGA VCCINT/ VCCAUX/MGTAVCC/VCCO or other critical supplies and the suitable impedance and DC resistance for them. I have not seen Beads on the FPGA supplies , can you please refer to some design. but i have seen beads of 600 ohm or 220 ohm impedance in some boards on other supplies(other than those mentioned above).
09-05-2012 08:33 AM
Suggest you begin a new thread to discuss your board design, a subject which is entirely unrelated to this thread.
-- Bob Elkind