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Registered: ‎05-19-2009

Spartan-3E (PQ208, XC3S500E) on two-layer PCB?



I am designing a FPGA-based signal processing unit with ADCs and DACs (about 1MSPS sampling rate, max. 32MHz to 50 MHz SPI data clock rate). The system will be clocked by a 50MHz oscillator (internally increased to 150MHz by a DCM). The first prototype was designed as extension to the Spartan-3E Starter-Kit, now I am designing the complete system. Unfortunately I have to use the PQ208 package as we are not able to solder BGA-packages. The PCB only has two copper-layers (top/bottom) where the bottom layer will be mainly used as groundplane.


Now I have got some questions:

  1. Is it possible to use the PQ208-package on a two-layer PCB?
  2. Where should I place the decoupling capacitors? Currently I am planing to use a 1nF and a 47nF ceramic cap for each supply pin (as in the Spartan-3E Starter-Board), a 470nF ceramic cap as well as a 10uF tantal cap for each VCCO-bank, VCCINT and VCCAUX. When I place the caps (especially the 1nF/47nF) directly at the supply pins on the top layer (where the FPGA is), I am blocking the access to I/O-pins. But when I place them on the bottom side and use two vias and traces for connection to the FPGA this increases the inductance.
  3. Do you have a recommendation how I should route power supply?
  4. Are there any important things I should consider under these circumstances?

Thanks for any help in advance.

Best regards,


Message Edited by milindur on 10-30-2009 04:41 PM
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4 Replies
Registered: ‎08-14-2007

I imagine your end product is cost sensitive or else you wouldn't consider a 2-layer board,

however I believe you're asking for trouble with high-speed logic on two layers.  If the

board must be 2 layers because it has a large area for other slow stuff, you might

consider a module for the Spartan.  There are some examples on the Enterpoint

website, for example the Darnaw1 with a pin grid array footprint and all decoupling

on board.


If your board is relatively small, the cost to go to 4 layers may be less than you think

and in my opinion worth the difference.  You REALLY want to have a solid ground

plane and the 4-layer would allow your bypass components to go on the back

of the board.  In addition, using the other inner layer as a split plane for power

gives some additional high-speed decoupling you won't get with any amount of

capacitors on a two-layer construction.




-- Gabor
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Registered: ‎06-12-2009

My guess is that you can get away with 2 layers if your bottom layer is not too broken up, and your bypassing is good.  But with only 2 layers it is hard to get a ground plane that's not like swiss cheese. 


We did a 3E-500 PQ208 design using a 4 layer board, with a 0.1uF ceramic cap per power pin a couple of years ago and it worked well.  Put caps close to the pins, use heavier traces for power.  One big cap like at least 10uF low ESR somewhere on board for each voltage.  Just basic good layout practice.


I found that the 1.2V core generated a fair amount of hash, so bypass that well and keep it away from your analog side.  One thing I found really effective for decoupling is small ferrite beads.    We used Steward MI1206K601R-10 which are 1206 case size.


We just did a design with a 3A-700 in FT256 BGA package - the BGAs are not that bad and there are many board houses now that will solder and xray them for you, even small quantities ... you can put on the rest of the parts yourself.  The ball spacing is 1mm which gives you enough room to run a trace between.





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Registered: ‎06-28-2012

Dear Jimbrady


can you or someone else explain how to select the beads to use for the FPGA VCCINT/ VCCAUX/MGTAVCC/VCCO or other critical supplies and the suitable impedance and DC resistance for them. I have not seen Beads on the FPGA supplies , can you please refer to some design. but i have seen beads of 600 ohm or 220 ohm impedance in some boards on other supplies(other than those mentioned above).



best regards



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Registered: ‎07-21-2009



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