07-21-2010 05:58 PM
I'm trying to write a vhdl code to let 2 spartan 3e to communicate via RS-232 so I have following questions and will appreciate it if you give me some heads up:
07-21-2010 11:44 PM
1. Get yourself a copy of the EIA/RS-232 Standard.
If you can't get the original paper, here's a nice page to read:
Get yourself some UART Core. A simple but nicely working one can be found bundled with the KCPSM3 (Picoblaze 3) design files, together with some documentation on how to use it. You can use it independently of the PicoBlaze.
2. Never ever, and how anyway. RS-232 is not using differential pairs. RS-422 and RS-485 do, but probably on different voltage levels than LVDS.
3. You said you want to make a RS-232 connection. and in point 4 you also mention the DB9 Connectors.
Have a look at the board schematics. between the Connectors and the FPGA you will most likely find some level shifting devices like MAX232 or something alike. This is the limiting factor. Any FPGA from plain old XC3000 to the arising Virtex 7 can deal with it, so don't bother about it here.
4. Sure you can. UART cores are quite small and 2 of them fit easily even into the smallest FPGA available. You can send bidirectional at the same time because transmitter and receiver of the UART are working independently of each other. So if you set up some simple circuit that sends data via both interfaces and compares that with the received data a simple LED can show you wether things are going well or not.
So you see, RS-232 is quite simple, but what made you think that LVDS has anything to do with it? What's your intention?
While RS-232 is a slow but reliable and highly compatible interface (works even with some of the oldest computers), LVDS is designed to transmit data way beyond 100MBaud therefore using reduced voltage leves and differential pairs. Two totally different things.
Have a nice synthesis
07-22-2010 02:11 AM
I really thank you for your advice and comments. I'm not exactly sure about few of things such as "UART Core". What is it and how can I get it and from ?
Regarding your questions on LVDS is because I need to transfer signal of type LVDS on a Virtex board but I was thinking to take some baby steps to learn it on SP3E then move onto Virtex-4 board.
I'm gald you confirmed about MAX3232 on FPGA board so I guess I shouldn't be worry about level shifting.
I hope you answer my questions as I go on this project.
Once again thank you and looking forward to learn from you more.
07-23-2010 12:10 AM
so, as expected you are talking about two different things.
Ok, lets sort it out.
RS232: It's a standard that describes the signaling and pinout used for asynchonous data transfers.
The circuit that converts your data into the asynchronous serial bitstream is called a UART. (Universal Asynchronous Receiver Transmitter). As mentioned befor there is one available in the KCPSM3 design files, and can be downloaded from the xilinx pages.
It's a good thing for connecting an FPGA Board to a computer. e.g. for terminal outputs. Due to the limitations of the MAX232 it has a low transfer speed of up to 100k baud.
LVDS: Also just a signal level definition, but not as specific as RS232, mor like TTL or CMOS level descriptions. So unless you don't define what kind of interface you intend to build, you can do almost anything with these lines, just like you would with any other o/Os on the FPGA. Only rule that applies is that the other end has to use the same I/O standard.
Some interface types that use LVDS (or compatible standards) are DVI-D, HDMI, CameraLink and probably PCI-E.
Any of these has a defined set of pins and a data protocoll. Special cores are needed to meet these requirements.
Of course you are free to specify an interface of your own, that uses LVDS level signals.
So what can you do? (What do you want to do?)
While LVDS is designed for high data rates it can be used with low data rates too.
The S3E and Virtex2/4/etc. are capable of driving and receiving LVDS levels on special paired I/O-pins.
See the datasheet pin assignment tables for details.
Check your board schematics if they are available on some generic connector (NOT the DB9 Com Ports!), so you can loop them back to the FPGA.
Then you are able to use the UART at any possible speed to transfer data via this connection.
Thus you are using a single LVDS signal way under it's intended and possible datarate, still you have implemented it and can do measurements and other tests.
Once you have an interface specification that makes use of the LVDS datarate you can start to design the appropriate core for this interface.
Have a nice synthesis