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Voyager
Voyager
2,748 Views
Registered: ‎08-30-2007

Spartan-3E ifd_delay_value input delay ISE 9.2

The Spartan-3E data sheet (pg 12) shows that the input delay consists of

a coarse delay and a fine delay line.  In using IFD_DELAY_VALUE in my

ucf file  (ISE 9.2), it looks like every setting must enable the coarse delay,

so the 1st step from delay=0 to delay=1 is a huge step.  Here are my

some results from the post-PAR timing report:

    IFD_DELAY = 0
        Y6.ICLK1             Tiopick               2.540   PHY_Rx_dv
    IFD_DELAY = 1
        Y6.ICLK1             Tiopickd              5.504   PHY_Rx_dv
    IFD_DELAY = 2
        Y6.ICLK1             Tiopickd              6.081   PHY_Rx_dv

    IFD_DELAY = 3

        Y6.ICLK1             Tiopickd              6.768   PHY_Rx_dv

    IFD_DELAY = 6
        Y6.ICLK1             Tiopickd              9.485   PHY_Rx_dv
    IFD_DELAY = 7
        Y6.ICLK1             Tiopick               2.540   PHY_Rx_dv
    IFD_DELAY = 8
        Y6.ICLK1             Tiopick               2.540   PHY_Rx_dv

 

Note that delay values of 7 and 8 revert back to  the same delay as 0!

 

AR #31906 has a link to a diagram that does not match my experimental results.

Another AR indicates that delays of 7 and 8 are allowed, other information says

that only 0 to 6 are supported.

 

So, is there a way to disable the coarse delay and allow the fine delay?

 

Thanks!

 

John Providenza

 

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Professor
Professor
2,735 Views
Registered: ‎08-14-2007

ug331 seems to imply that the coarse delay is independent of the 6-tap delay line.

I tried to look at this in ISE 11.5 and got the error:

 

ERROR:NgdBuild:995 - Line 17 in s3e_ifd_delay_top.ucf: Constraint
   'IFD_DELAY_VALUE' has a value '10' which is invalid. Use the following:
   The value must be an integer with units >= -1 and <= 8

 

 So I tried a simple project with delays -1 through 8 using the following ucf code:

 

NET "d_in<0>" IFD_DELAY_VALUE = 0;
NET "d_in<1>" IFD_DELAY_VALUE = 1;
NET "d_in<2>" IFD_DELAY_VALUE = 2;
NET "d_in<3>" IFD_DELAY_VALUE = 3;
NET "d_in<4>" IFD_DELAY_VALUE = 4;
NET "d_in<5>" IFD_DELAY_VALUE = 5;
NET "d_in<6>" IFD_DELAY_VALUE = 6;
NET "d_in<7>" IFD_DELAY_VALUE = 7;
NET "d_in<8>" IFD_DELAY_VALUE = 8;
NET "d_in<9>" IFD_DELAY_VALUE = -1;
NET "d_in<10>" IFD_DELAY_VALUE = 0;
NET "d_in<11>" IFD_DELAY_VALUE = 1;
NET "d_in<12>" IFD_DELAY_VALUE = 2;

 

(originally these were 0 to 12)

 

Here's the timing datasheet report:

 

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |Max Setup to|Max Hold to |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
d_in<0>     |   -0.302(R)|    1.906(R)|clk_BUFGP         |   0.000|
d_in<1>     |    2.020(R)|   -0.394(R)|clk_BUFGP         |   0.000|
d_in<2>     |    3.150(R)|   -0.820(R)|clk_BUFGP         |   0.000|
d_in<3>     |    4.012(R)|   -1.220(R)|clk_BUFGP         |   0.000|
d_in<4>     |    4.417(R)|   -1.654(R)|clk_BUFGP         |   0.000|
d_in<5>     |    4.853(R)|   -2.072(R)|clk_BUFGP         |   0.000|
d_in<6>     |    5.696(R)|   -2.449(R)|clk_BUFGP         |   0.000|
d_in<7>     |   -0.280(R)|    1.881(R)|clk_BUFGP         |   0.000|
d_in<8>     |   -0.301(R)|    1.906(R)|clk_BUFGP         |   0.000|
d_in<9>     |    3.156(R)|   -0.828(R)|clk_BUFGP         |   0.000|
d_in<10>    |   -0.303(R)|    1.908(R)|clk_BUFGP         |   0.000|
d_in<11>    |    2.038(R)|   -0.414(R)|clk_BUFGP         |   0.000|
d_in<12>    |    3.149(R)|   -0.819(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

 

Seems to confirm your findings.  Also I'm not sure what -1 is supposed to do.

 

regards,

Gabor

 

 

-- Gabor
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