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Newbie ruiter401
Newbie
9,132 Views
Registered: ‎03-05-2009

Spartan 3E startup with m25p80,

The problem:

 

The fpga does not start up by manual reset after it is flashed using SIP interface - through the fpga.

 

Startup procedure; starting from scratch:

- Impact together with platform cable USB II is used to flash the m25p80 through the Spartan 3E fpga .

 

code:

setMode -bs
setCable -port usb21
setMode -bs
identify
assignFile -p 1 -file "D:/xilinx/ecb/daniel/bp3_4/bp3.bit"
attachflash -position 1 -spi "M25P80"
assignfiletoattachedflash -position 1 -file "D:/xilinx/ecb/daniel/bp3_4/bp3.mcs"
Program -p 1 -spionly -e -v
Checksum -p 1 -spionly
quit

 

- This works, fpga is running, flash can be written. CRC flash is OK.

 

 

- Reset power off/on, or reset button will not start the fpga from reading flash, clk looks fine no overshoot.

 

Looking in more detail; we came up with a solution; adding 5pF near fpga on the CClk pin.

This is fine for lab experiments, but we want a reliable solution ==> always working! (vs temp, voltage variation, tolerance, etc)

 

So what is the mechanism why it does not work without 5pF?  Does XILINX/anyone have a reliable solution?

 

 

 

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6 Replies
Xilinx Employee
Xilinx Employee
9,126 Views
Registered: ‎07-25-2008

Re: Spartan 3E startup with m25p80,

Hi there,

 

This sounds like a signal integrity issue.

 

You said: Reset power off/on, or reset button will not start the fpga from reading flash

Does that mean you see no activity on the SPI signals?

 

Do you see INIT go low after the reset button? This would indicate a CRC error.

A good way of checking this is to read back the status register of the FPGA after you try to configure it.

To read back the status register:
-          open impact
-          initialize chain
-          Debug --> Read Device Status

Could you post the status register here?

 

What is the bandwidth of the scope you used to measure the CCLK signal?

And do you have some sort of termination for CCLK on the board?

 

 

Cheers!

 

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Newbie ruiter401
Newbie
8,999 Views
Registered: ‎03-05-2009

Re: Spartan 3E startup with m25p80,

After more debugging we found out that problaby the on-chip RC clock circuit is designed on its limit. The fpga starts up when the chip is cooled to -40 deg, also when it is heated above +40deg. We are waiting on a response of Xilinx.

 

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Historian
Historian
8,994 Views
Registered: ‎02-25-2008

Re: Spartan 3E startup with m25p80,


ruiter401 wrote:

After more debugging we found out that problaby the on-chip RC clock circuit is designed on its limit. The fpga starts up when the chip is cooled to -40 deg, also when it is heated above +40deg. We are waiting on a response of Xilinx.

 


Are you sure that the VS[2:0] pins are set correctly for your particular SPI EEPROM?

 

See XAPP951 -- Configure FPGAs With SPI Serial Flash.

 

-a

----------------------------Yes, I do this for a living.
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Explorer
Explorer
8,990 Views
Registered: ‎11-07-2008

Re: Spartan 3E startup with m25p80,

Hi,

I was having a similar problem, so I brought the Configuration rate (CCLK freq) down to 6 MHz from 25 MHz, this solved the configuration  PROM from on Power-On reset. You may want to try it.

I am still fighting the other one though, where in it doesnt configure after a manual reset (from an on board switch) is applied.

 

Shax

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Newbie ruiter401
Newbie
8,970 Views
Registered: ‎03-05-2009

Re: Spartan 3E startup with m25p80,

The clock (CCLK) is currently running on 50MHz, we tried speeding up / lowering down the clock without the resistors, but this did not help.

 

We have solved it by adding two 100E resistors at the pin of the flash, one to gnd; the other to vdd of the flash.

This worked under all temperatures. Now multiple boards are being assembled to see if there is a spread issue.

 

 

 

 

 

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Xilinx Employee
Xilinx Employee
8,965 Views
Registered: ‎07-25-2008

Re: Spartan 3E startup with m25p80,

Hi there,

 

Good to hear that terminating the line solved the problem!

 

The problem with lowering the frequency is that you won't necessarily  get rid of your SI problems.

It is really more the fast rise time of the signal that causes the problems.

The rise time will stay the same even if the CCLK frequency is lowered.

 

 

Good luck for your project!

 

 

Cheers!

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