We have a design which inputs 14 bit + clock in differential lvds DDR format from an external 250 MSPS ADC. The logic chain was originally created by coregen and each path includes an IODELAY2. We have found that it is not necessary to use the IODELAY2 capability so, to reduce timing varability, it seems like a good idea to remove them. However, just deleting and connecting the delay input to output signals together causes a map exception which reports that BUFGs needed in the clocks path are in very sub-optimum positions. If the BUFGs are also eliminated the design then compiles but fails to achieve timing closure even with Smart Explorer.
The clocks paths are IBUFGDS_DIFF_OUT > 2 x ( IDELAY2 > BUFG) > IDDR2
The data paths are IBUFDS > IDELAY2 > IDDR2
Any suggestions please?
