06-29-2017 05:04 AM
I’m working on a design on Spartan 6.
Data is coming from PCIe IP Core at 62.5MHz clock and passes through AXI4-Stream FIFO to synchronize into 100 MHz system clock.
Here is an example waveform;
Isn’t clock domain clock synhronization handled within FIFO IP Core and whenever m_axis_tvalid is high it means there is stable data in FIFO so when i pull m_axis_tready high transcation happens?
Is it normal that data keeps changing altough m_axis_tvalid is high?
Is my understanding of AXI4-Stream FIFO incorrect?
The version of AXI4-Stream FIFO i’m using is LogiCORE IP FIFO Generator v9.3
I've attached the png in case it's not clear
06-29-2017 05:15 AM
Both are normal.
You'll notice that the TVALID signal is actually synchronized to the 100MHz clock (in that it always has the same phase relative to the 100MHz clock) - it's just not changing on the clock edge. This is because the block RAM used for the FIFO takes a little bit of time after the clock edge to provide its data. It should have no effect on functionality.
For your second point, that is exactly how flow control is meant to work for an AXI Stream. Whenever TVALID and TREADY are both high on a rising clock edge, one data element is transferred. Once this element has been transferred, another one appears on the port, ready to be transferred at the next clock edge. If it could only change the data when TVALID was low, then it would have to pull TVALID low for one cycle after each data element was transferred - resulting in a maximum throughput of one data element every second clock cycle.
06-30-2017 05:44 AM
Thank you for reply,
But i cannot read data correctly. If you notice m_axis_tdata for the second sample is stable for a very short time (less then a clock cycle) and when i sample it on the rising edge of the clock it reads some garbage value because data is constanty changing.
What sould i do here? Lower the speed i'm reading? As you see i keep m_axis_tready constantly high. Should i pull it down for one cycle after a valid read?