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7,680 Views
Registered: ‎07-28-2011

Spartan 6 BUFIO's, OSERDES, strobea and strobeb

This is in relation to XAPP1064, pg 17 on a Spartan 6 LX45

 

When using 4 BUFIO2's in one bank to enable the whole side of a device to be driven. What determines the phase of the Serdes strobea for one bank relitive to the other bank strobeb? Is there any way to ensure the phases of these are aligned so that the data is outputted in the same phase?

 

Background: I am outputting a serial 14bit LVDS stream over to halfs of the same bank at 1GSPS. I seem to be getting a phase difference between the two halfs of the bank which seems to be dependant on when the clock into the BUFIO2's starts up. Do I need to make sure there is a clock applied to the BUFIO2's on the configuration of the spartan 6 (I configure the clock from the spartan 6 which could be causing problems)?

 

Are there any example designs that are out there for configuring both halfs of the FPGA for OSERDES in the same bank.

 

Thanks, Matt

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8 Replies
Xilinx Employee
Xilinx Employee
7,674 Views
Registered: ‎08-21-2007

Re: Spartan 6 BUFIO's, OSERDES, strobea and strobeb

Are the data/clock signals of the same trace length? I suggest a training pattern running on all the 14-bit lvds pins and check if  correct patterns are at ISERDES output. Adjust IODELAY and BitSslip to make it happen.

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Teacher eteam00
Teacher
7,669 Views
Registered: ‎07-21-2009

Re: Spartan 6 BUFIO's, OSERDES, strobea and strobeb

Kathy, I believe the application is for serial output rather than serial input.

 

-- Bob Elkind

SIGNATURE:
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Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
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7,638 Views
Registered: ‎07-28-2011

Re: Spartan 6 BUFIO's, OSERDES, strobea and strobeb

Sorry for the long time to reply. Yes bob you are correct it was for an SERDES OUTPUT application. In interest of closing the post I started and not leave it hanging there, here is the answer to my question.

 

It seems that the BUFIO2's require a stable clock on configuration of the FPGA. Because I was reconfiguring the external clock going to the BUFIO2 this would put the bufio strobe signals out of alignment between the two ouput sides of the bank. To solve this problem I had to get the FPGA to reconfigure itself on the fly after it configured the external clock, not the best solution but it seems to solve the jitter bettween the sides of the bank. I don't know if there is another way to align the bufio2 strobe signals, maybe someone has a better solution?

 

Also there does not seem to be any meantion of this bufio2 clock alignment between banks in any datasheets I could find, maybe it would be a good thing to include, or at least meation that the clocks should be stable before configuring one?

 

-- Matthew van der Werff

Teacher eteam00
Teacher
7,636 Views
Registered: ‎07-21-2009

Re: Spartan 6 BUFIO's, OSERDES, strobea and strobeb

In a thread with similar problem, the recommended solution was to use one (and only one) of the DIVCLK outputs to drive *all* ISERDES (or OSERDES) blocks in all IO half-banks, and drive the global fabric clock as well.

 

Give this a try.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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7,627 Views
Registered: ‎07-28-2011

Re: Spartan 6 BUFIO's, OSERDES, strobea and strobeb

Thanks for the reply Bob. I did previously try some of the suggestions previously in that discussion, and I do drive both banks from the same divclk. This may solve the problem of the div clocks being correctly aligned but does not solve the problem that the BUFIO2 STROBE signals are out of alignment between the bank half's. This causes a data output misalignment, as the bus data is latched into their respective SERDESO elements (via the strobe signal) at different times. So creating a data misalignment between the half banks by up to 7 clock cycles (at 1GHz).

 

-- Matthew van der Werff

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Teacher eteam00
Teacher
7,624 Views
Registered: ‎07-21-2009

Re: Spartan 6 BUFIO's, OSERDES, strobea and strobeb

This may solve the problem of the div clocks being correctly aligned but does not solve the problem that the BUFIO2 STROBE signals are out of alignment between the bank half's. This causes a data output misalignment, as the bus data is latched into their respective SERDESO elements (via the strobe signal) at different times. So creating a data misalignment between the half banks by up to 7 clock cycles (at 1GHz).

 

Understood and agreed.

 

Suggestions/Options:

 

1.  Open a webcase.  Post the official Xilinx response for all to read.

 

2.  Do nothing, place the burden for word framing on the serial receiver(s).

2.a  Use the TRAIN feature of the OSERDES2 to help the receiver with word framing.

2.b  Provide a dedicated word framing serial output pattern for the receiver to use.

 

3.  Assign (group) all the serial outputs which must have matched (+/- 1 bit) word alignment on a single BUFIO2 region.

 

4. Don't use BUFIO2.  Use PLL + BUFPLL instead.  BUFPLL self-aligns SERDESSTROBE to global clock

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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7,621 Views
Registered: ‎07-28-2011

Re: Spartan 6 BUFIO's, OSERDES, strobea and strobeb


@eteam00 wrote:

This may solve the problem of the div clocks being correctly aligned but does not solve the problem that the BUFIO2 STROBE signals are out of alignment between the bank half's. This causes a data output misalignment, as the bus data is latched into their respective SERDESO elements (via the strobe signal) at different times. So creating a data misalignment between the half banks by up to 7 clock cycles (at 1GHz).

 

Understood and agreed.

 

Suggestions/Options:

 

1.  Open a webcase.  Post the official Xilinx response for all to read.

 

2.  Do nothing, place the burden for word framing on the serial receiver(s).

2.a  Use the TRAIN feature of the OSERDES2 to help the receiver with word framing.

2.b  Provide a dedicated word framing serial output pattern for the receiver to use.

 

3.  Assign (group) all the serial outputs which must have matched (+/- 1 bit) word alignment on a single BUFIO2 region.

 

4. Don't use BUFIO2.  Use PLL + BUFPLL instead.  BUFPLL is self-aligns SERDESSTROBE to global clock

 

-- Bob Elkind


Thanks for that advice bob, replies below.

1) Have not done this, where do you post this?
2) Good idea but since I am comunicating with a High Speed DAC I with fixed logic I do not have this luxary.
3) All bits need to be aligned in this case of the DAC I am using, so will not work.
4) Tried this but the PLL + BUFPLL as far as I am aware does not support speeds as high as 1000Mbs.
-- Matthew van der Werff
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Teacher eteam00
Teacher
7,619 Views
Registered: ‎07-21-2009

Re: Spartan 6 BUFIO's, OSERDES, strobea and strobeb

1) Have not done this, where do you post this?

 

There are a number of click sequences which can get you to the webcase page, but it's easier to simply tell you to

just click here and from there, click on one of the 'Quick Links' to the right.

 

2) Good idea but since I am comunicating with a High Speed DAC I with fixed logic I do not have this luxary.

3) All bits need to be aligned in this case of the DAC I am using, so will not work.

 

Pity the poor circuit board designer.  No framing logic in the DAC for multiple 1Gbit/sec serial inputs?  I hope you are very well paid!

 

4) Tried this but the PLL + BUFPLL as far as I am aware does not support speeds as high as 1000Mbs.

 

DS162, Tables 25, 51, and 52, rated for 1080MHz (1080Mb/sec), -3 speed grade.

-2 speed grade is good for 950MHz (Mb/sec).  Does this settle the matter?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.