Spartan-6 DSP48A1 more detailed switching characteristics?
Does anyone know if there are more detailed switching characteristic information for the Spartan-6 DSP48A1 (-2 speed)? Some numbers I would like to know are:
1. maximum clock frequency from A0-reg to P-reg with no intervening registers, with and without using the post-adder.
2. data setup times to A0 and B0. Are they same as for A1 and B1?
3. M-reg to MFOUT prop delay from clock
4. maximum clock frequency from A0-reg to M-reg to P-reg, bypassing A1-reg, with and without using the post-adder.
5. A-reg, B-reg, or C-reg to P out without using the post-adder.
6. PCIN data setup time to P-reg with post-adder (at least as good as using C-reg?, but it doesn't actually say).
It's hard to architect a pipelined design for maximum speed without knowing these times at the start. I've made some assumptions, designed a pipeline, and ISE told me my design is inherently too slow. I don't like to find out the fastest approach by trial-and-error.