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4,704 Views
Registered: ‎11-22-2016

## Spartan 6 FPGA - LUT

Hello all,

Say if I want to realize a simple "and" gate using a spartan 6 FPGA. I understand the "and" gate will be emulated into the Look Up Table. Can someone shed more light on this?.

Does the and gate truth table gets ported to the LUT?

Does the LUT's have pmos and nmos transisors inside them?

Spartan 6 has 6 input LUTs, so if I want to realize a simple two input "and " gate..what happens to the other four inputs?

Thanks,

Manoj

1 Solution

Accepted Solutions
7,733 Views
Registered: ‎04-26-2015

(1) Yes, the AND gate truth-table will get mapped into a LUT.

(2) Xilinx is probably not going to tell us exactly how their LUTs are constructed electrically. Suffice to say that they're 64-element, 1-bit SRAMs.

(3) They just get ignored. For a 4-input lookup table the truth table would be:

```0000 : 0
0001 : 0
0010 : 0
0011 : 0
0100 : 0
0101 : 0
0110 : 0
0111 : 0
1000 : 0
1001 : 0
1010 : 0
1011 : 0
1100 : 1
1101 : 1
1110 : 1
1111 : 1```

(ie whenever the first two bits are set, the output is 1; otherwise it's zero). A six-input LUT will be exactly the same, but with 64 entries instead of 16.

Tags (2)
5 Replies
7,734 Views
Registered: ‎04-26-2015

(1) Yes, the AND gate truth-table will get mapped into a LUT.

(2) Xilinx is probably not going to tell us exactly how their LUTs are constructed electrically. Suffice to say that they're 64-element, 1-bit SRAMs.

(3) They just get ignored. For a 4-input lookup table the truth table would be:

```0000 : 0
0001 : 0
0010 : 0
0011 : 0
0100 : 0
0101 : 0
0110 : 0
0111 : 0
1000 : 0
1001 : 0
1010 : 0
1011 : 0
1100 : 1
1101 : 1
1110 : 1
1111 : 1```

(ie whenever the first two bits are set, the output is 1; otherwise it's zero). A six-input LUT will be exactly the same, but with 64 entries instead of 16.

Tags (2)
Xilinx Employee
4,680 Views
Registered: ‎09-05-2007

I'm a great believer in engineers having an underlying appreciation of how something is actually implemented because engineers with that knowledge can definitely implement better (I.e. lower cost, higher performance, lower power) designs even when using tools at higher levels of abstraction. I therefore like your questions but also wonder why you are asking them.

As 'u4223374' indicated, there is little point considering how a LUT is implemented in the actual silicon. As a user you can influence how many LUTs are used and the pattern of bits within each LUT. You cannot influence the choice of transistors or how they switch etc.

The example of a 4-input LUT given by 'u4223374' is correct and assumes that the most significant 2-bits of the LUT address (i.e. its inputs) are being used. In practice, any 2 inputs can be used providing the bit pattern in the look up table is suitably adjusted. Just as you can assign which inputs are used, the tools can change which inputs are used. This provided more options for the routing of a design by allowing convenient inputs to LUTs to be used for each signal (providing the bit pattern is changed to reflect any pin swapping).

Less obvious is the opportunity to replicate the bit pattern. Using the example given by 'u4223374' we can see that the 4-bit pattern actually required has been replicated 4 times as this allows the 2 unused inputs to have any values. This in turn means that it does not matter if the unused inputs are collected to '0', '1' or even something changing state; the output value will only depend on the two inputs of interest.

Ken Chapman
Principal Engineer, Xilinx UK
Tags (1)
4,657 Views
Registered: ‎11-22-2016

Thanks for your reply Chapman. I had these questions in my mind primarily for the following reason.

1. If FPGAs implement gates as LUTs and the gate structure is gonna be different electronically, then how do they use FPGAs to prototype ASICs?.

Was also curious on how it get implemented in a deeper level.

Thanks,

Manoj

Xilinx Employee
4,648 Views
Registered: ‎09-05-2007

In that case, this can be the topic for an interesting debate. Before I make a few potentially controversial comments, I do want to make it clear to you and other readers that the logical function that a LUT implements is only limited by its number of inputs. Therefore, a LUT will typically implement the equivalent of multiple 2-input gates; the complexity of the function doesn’t matter at all. A simple but good example is that of a 4:1 multiplexer that fits nicely in a single 6-input LUT because it had 4 data inputs and 2 select inputs. If we consider a 4:1 multiplexer to be formed of three 2:1 multiplexers, then with each 2:1 multiplexer the equivalent of (at least) 3 gates, the LUT6 would be implementing 9 gates.

So when an FPGA is used to emulate an ASIC it is generally just a case of implementing the ASIC design in an FPGA with as many or as few gates being placed into each LUT as possible. The ability for the tools to do this optimally could well be compromised by the desire to have ‘probe points’ (i.e. you can’t observe the output of a gate if it is merges with others into LUT and that may result in less packing). This use of an FPGA for emulation is really no different to a simulation model on a computer; the objective is to EMULATE the end product without having to fabricate it thereby saving a lot of money and time. The key advantage of using an FPGA is that it will be emulate much faster than a simulation model; often at full speed allowing the emulation/simulation to be tested in real time and scenarios.

Now for my potentially controversial comments…

As far as I’m concerned, an FPGA is not an ASIC. Yes, it can easily emulate one but it is a programmable array of flexible but pre-defined set of building blocks. If a design is created to target the use of those building blocks then ‘emulation’ is no longer playing a part and we have a more direct mapping and usage of the architecture. The net results are designs implemented using less resources resulting lower cost, higher performance and lower power consumption. It is my personal opinion that a large number of engineers are creating designs without consideration of the target architecture (ASIC or FPGA) and therefore require the FPGA to ‘emulate’ what they have described. If their description isn’t a natural fit with the building blocks then the emulation of what they have described will use more resources. If they have described functions that are a more natural fit with the architecture then their design will fit well.

Put simply, the best engineers create designs that are sympathetic to the intended target architecture and are rewarded with good results. But here’s the observation; a design that is ideally suited to an ASIC probably isn’t going to be ideally suited to an FPGA and vice versa. Let’s consider a few reasons. In an ASIC we would want to minimise gates and levels of gates but in an FPGA it’s the number of inputs to a function that counts. In an ASIC we probably have a wide selection of flip-flop types but in an FPGA we have only one. Of course it is a programmable flip-flop but, for example, the reset always has priority over clock enable so did the design reflect that or not? An ASIC designer must also consider how the device will be tested in production and this brings me to one of my all-time favourite topics; the ‘global asynchronous reset’ so often found in design code. Unlike an ASIC, and FPGA is 100% tested before it is shipped and configuring the device initialises everything including all BRAM contents. Therefore an FPGA design does not need a global reset and without one a design is smaller, faster and consumes less power.

I’m not saying that engineers should not exploit the capability of today’s FPGAs; if FPGAs facilitate getting a product to market quickly and a less than optimum implementation is good enough to meet cost, power and performance targets then that’s fine. What I personally have issues with are when the design implementation style is not questioned in cases where the targets are not met or when someone looks at how big the emulation of an ASIC design is in an FPGA and assumes FPGA technology can never replace an ASIC. All of this has happened before in the computer/processor industry so it should not be a surprise. When computers had a few K-bytes of memory and tape drives for storage the programs had to be very well crafted to the architecture. Now with G-Bytes of RAM and T-Bytes of blink-of-the-eye storage there is much more emphasis on getting the product out there than worrying about how well the resources are used. Well, that’s until it’s a smart phone that needs to be charged every 2 hours and then everyone wonders how to make one that will consume less power!

Ken Chapman
Principal Engineer, Xilinx UK
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