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Registered: ‎11-01-2011

Spartan 6 IO Bank Voltage and IOStandard in UCF

I have an input signal that is 1.8V CMOS that is connected to an IO bank that is tied to 3.3V.

 

If I specify the IOSTANDARD as LVCMOS18 in the UCF, will it trigger at 1.8V CMOS levels or are all IOs on that bank triggred at 3.3V CMOS levels?

 

All other signals on that bank are 3.3V CMOS signals.

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Scholar
Scholar
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Registered: ‎02-27-2008

m,

An IO bank's thresholds for LVCMOS standards are set by the Vcco value. So, the threshold for 1/0 is Vcco/2.

A 3.3 volt bank will switch LVCMOS standards at 3.3/2=1.67v.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

In Spartan-6 an input that use the LVCMOS18 IOSTANDARD is not tied to the VCCO level, so it can be placed in a bank with a VCCO of 3.3V.  If the LVCMOS18_JEDEC IOSTANDARD is used then the VCCO level most be 1.8V.

 

See Table 7 of the Spartan-6 data sheet DS162.

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Scholar
Scholar
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Registered: ‎02-27-2008

Ed,

I keep forgetting that S6 has all those "strange and odd features."

Thanks for the correction,

Austin Lesea
Principal Engineer
Xilinx San Jose
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