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efly_zhao
Observer
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Registered: ‎04-04-2018

Spartan-6 IO

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Hi, I have 2 questions below.

 

1. Does the Spartan-6 IOs have built-in schmitt triggers?

 

2. I did notice the clock output generated from FPGA has higher jitter than a external clock distributor. But why does it happen?

 

Thank you very much.

 

Yifei

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bruce_karaffa
Scholar
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Registered: ‎06-21-2017

 

You are correct, an FPGA will generally add jitter to a clock and Xilinx does not recommend using an FPGA to drive a precision ADC or DAC.  I'm not a Xilinx employee so I can't explain in detail, but an FPGA is a large digital switching network with a complex clock distribution system.  Specialized clock distribution chips tend to limit internal switching and have a large number of power and ground pins compared to the number of outputs.  They will be quieter internally, inducing less clock jitter.  If you really want to talk jitter in an FPGA, hope that chimes in. 

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bruce_karaffa
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Scholar
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Registered: ‎06-21-2017

A search of UG381 Spartan-6 FPGA SelectIO Resources User Guide does not find "schmitt".  You would normally need a schmitt trigger for a slowly changing, noisy input.  I suggest that there other ways to handle these in an FPGA, say something similar to a debouncing circuit.

 

Do you mean a clock generated by the FPGA or a clock passed through the FPGA.  Any method of generating a clock in an FPGA will be inherently jittery.  If you mean passed through the FPGA, some jitter will be added.  How much depends on the circuit.  Did you use dedicated clock routing?  Did you use a DCM or a PLL?  Did you forward the clock properly, using a DDR register or just running it straight to an output?  Is your FPGA properly decoupled?  Any power or ground noise will translate to jitter.

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efly_zhao
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Registered: ‎04-04-2018

Hi Bruce,

 

Thank you very much for the reply.

 

It is a 48MHz external clock input to Spartan 6 FPGA. Then this clock divided down to 24 MHz by PLL or DCM. A DDR register, i.e. ODDR2 is also used. Then this 24 MHz clock is sent to clock a DAC.  (basically I followed the recommendations in ug382). 

 

The DAC output has high jitter noise when using the 24 MHz clock from FPGA, but much lower jitter noise when using a 24 MHz clock from an external clock distributor.

 

I am curious on why it happens. Is it due to the way I generate this clock in FPGA, or the hardware design of FPGA board, i.e. signal integrity issue, or the clock generated from FPGA cannot clock the ADCs or DACs (Actually most commercial digital cards I used have an external clock distributor to clock ADC, DAC and FPGA sparately.) ? Thank you.

 

Yifei

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bruce_karaffa
Scholar
Scholar
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Registered: ‎06-21-2017

 

You are correct, an FPGA will generally add jitter to a clock and Xilinx does not recommend using an FPGA to drive a precision ADC or DAC.  I'm not a Xilinx employee so I can't explain in detail, but an FPGA is a large digital switching network with a complex clock distribution system.  Specialized clock distribution chips tend to limit internal switching and have a large number of power and ground pins compared to the number of outputs.  They will be quieter internally, inducing less clock jitter.  If you really want to talk jitter in an FPGA, hope that chimes in. 

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jheslip
Xilinx Employee
Xilinx Employee
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Registered: ‎06-30-2010

To address the initial questions:

 

1. Does the Spartan-6 IOs have built-in Schmitt triggers?

> No the last Xilinx device that had Schmitt triggers was the CoolRunner-II

 

2. I did notice the clock output generated from FPGA has higher jitter than an external clock distributor. But why does it happen?

> THe output jitter will depend on whether a DCM or PLL is used also the input clock.

 

If you have a very clean input clock lets say 50pS then you will get more jitter on the output clock as the PLL is more of a jitter filter. However, if you had 400pS you would get a much cleaner clock out.

 

The POwer rails also impact the jitter out on the clock so VCCINT VCCAUX and VCCO of the CLKIN and CLKOUT pins.

 

What is the jitter spec of the external clock?

The clock wizard will give the expected output jitter based on the PLL setup being used and the CLKIN jitter.

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alesea
Explorer
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Registered: ‎05-08-2018

Bruce,

 

Not at Xilinx - off to accomplish even greater things.  But yes, best practice in NOT to use the FPGA device resources for clock generation or distribution due to potential for added jitter.  Note that the Zynq RFSoC device is different as its clocking is hardened (designed) to meet the system jitter requirements.

 

Austin Lesea

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