I have a question concerning the Spartan 6 IODELAY2 element.
I would like to implement an 480 MSPS DDR interface with ISERDES factor 8. Therefore I used the SelectIO ip core wizard. The clock is forwared from the external via BUFIO2.
The wizard now instantiates the IODELAY2 in variable mode (which I want to use) for the data lines and uses the IOCLK0 and IOCLK1 for the clock derived from the BUFIO2. And there is an additional clock input named CLK in this IODELAY2.
In the FPGA datasheet there is a FMINCAL parameter mentioned which has to be at least 188Mbit/s. Does this relate to the IOCLK0 and IOCLK1? Which clock rate do I have to connect to the IODELAY2 CLK signal? Is this similar to Virtex 6, where it had to be a clock between 200 and 300 MHz? Or can I use the divided clock derived from the ip core too?