cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Anonymous
Not applicable
1,980 Views

Spartan 6 IOSTANDARD error for differential signal

Jump to solution

Hi,

 

I am using Spartan 6 eval board, SP605. I am trying to do something very simple here. Just want to route the differential system clock 200 MHz into FPGA and output to 2 LVDS pins so I can send them to clock a chip with LVDS interface.

 

I see this error 

 

Pack:2908 - The I/O component "CLKOUT_N" has an illegal IOSTANDARD value.
The IOB component is configured to use single-ended signaling and can not use
differential IOSTANDARD value LVDS_33. Two ways to rectify this issue are:
1) Change the IOSTANDARD value to a single-ended standard. 2) Correct the I/O
connectivity by instantiating a differential I/O buffer.

 

I double checked in the I/O Resources datasheet that bank 0 and 2 are used for LVDS outputs. I do not understand why I have this error. I attached the code here and also the UCF. 

Thanks ahead for any help.

 

 

library IEEE;
Library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use UNISIM.vcomponents.ALL;
use ieee.std_logic_unsigned.all;

-- IBUFDS: Differential Input Buffer
-- Spartan 6
-- Xilinx HDL Libraries Guide, version 13.4

 

entity init is
port(
CLKOUT_P : out std_logic ;
CLKOUT_N : out std_logic ;
CLKIN_P : in std_logic;
CLKIN_N : in std_logic
--DISABLE_P : out std_logic;
--DISABLE_N : out std_logic;
--RSTIDX_P : out std_logic;
--RSTIDX_N : out std_logic;
-- user_clk : in std_logic; -- 27 MHz external clk input to FPGA
-- -- SPI 4 wires
---- spi_miso : in std_logic; -- Master in, slave out, just put high impedance since we don't read anything here, read out from LVDS
-- spi_mosi : out std_logic; -- Master out, slave in, send config register values to TDC
-- spi_ssn : out std_logic; -- Slave select not, positive pulse to start, when LOW -> ready to shift of data in/out to/from device
-- spi_clk : out std_logic
);

end init;

architecture Behavioral of init is
component IBUFDS_DIFF_OUT
generic (
DIFF_TERM : BOOLEAN;
IBUF_LOW_PWR : BOOLEAN;
IOSTANDARD : string;
USE_IBUFDISABLE : string);


port(
O : out std_logic ;
OB : out std_logic ;
I : in std_logic ;
IB : in std_logic
);
end component;

begin
-- * Generate LVDS Clock output lines into TDC * --
CLKBUF_IN: IBUFDS_DIFF_OUT
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT", -- Specify the input I/O standard
USE_IBUFDISABLE => "TRUE"
)
port map (
O => CLKOUT_P, -- Buffer output positive
OB => CLKOUT_N, -- Buffer output negative
I => CLKIN_P, -- Diff_p buffer input (connect directly to top-level port)
IB => CLKIN_N -- Diff_n buffer input (connect directly to top-level port)
);

end Behavioral;

 

 

UCF file is

 

 

# 200 MHz LVDS clock input pair into FPGA
NET "CLKIN_P" LOC = "K21" | IOSTANDARD = LVDS_33;
NET "CLKIN_N" LOC = "K22" | IOSTANDARD = LVDS_33;

# Loop thru FPGA to output LVDS clock pair into TDC
NET "CLKOUT_P" LOC = "V11" | IOSTANDARD = LVDS_33; # FMC_LA21_P
NET "CLKOUT_N" LOC = "W11" | IOSTANDARD = LVDS_33; # FMC_LA21_N

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Mentor
Mentor
2,682 Views
Registered: ‎02-24-2014

Re: Spartan 6 IOSTANDARD error for differential signal

Jump to solution

This is more complicated than you need..   Use an ordinary IBUFDS on the input..  take the single ended output, and drive an OBUFDS differential output.    You can't use differential signalling inside the FPGA (mostly).   

Don't forget to close a thread when possible by accepting a post as a solution.

View solution in original post

2 Replies
Highlighted
Mentor
Mentor
2,683 Views
Registered: ‎02-24-2014

Re: Spartan 6 IOSTANDARD error for differential signal

Jump to solution

This is more complicated than you need..   Use an ordinary IBUFDS on the input..  take the single ended output, and drive an OBUFDS differential output.    You can't use differential signalling inside the FPGA (mostly).   

Don't forget to close a thread when possible by accepting a post as a solution.

View solution in original post

Highlighted
Anonymous
Not applicable
1,948 Views

Re: Spartan 6 IOSTANDARD error for differential signal

Jump to solution

Thank you so much. I got it to work!!!!!!!!

 

0 Kudos