08-24-2015 01:30 AM
I'm trying to use a Spartan 6 [XC6SLX45-2FGG484] to deserialize data from a TI AFE5851. The AFE is capable of sampling 16 at 32.5MSPS and sending serialised data DDR over 8 channels with bit clock and frame clock (all differential).
Starting from XAPP1064, and having read the UG381 documents, I'm using the BUFIO_DDR template. I have a data width of 8 channels and a deserialisation factor of 6. The files are as follows:
When I try to implement the design timing does not close if I try to achieve the anything above a clock of 10MSPS. From the AFE datasheet, I understand that the timing constraint should be specified as (at full speed):
TIMEGRP "datain_group_p" OFFSET = IN 0.65 ns VALID 1.25 ns BEFORE "clkin_p" RISING;
Attached are the files involved in project.
Am I specifying timing correctly (I got the same constraint using the constraints editor)? How fast can I go?
08-24-2015 07:40 AM
Generally speaking, if you are running at high bit rates you can't really meet any reasonable setup and hold timing at the inputs for a fixed clock phase. You would need to use one of the pattern modes of the AFE to train the link (adjust clock phase until you see the expected pattern). In this case, you can pretty much leave out the OFFSET IN constraints, because there is really no way the tools can do anything to meet it. Essentially your clock phase is variable, but the tools only work with one set phase. In addition, there is nothing the tools can manipulate to change the relative clock to data input timing when you use the ISERDES. So the tools have their hands tied, while trying to meet a constraint that isn't necessary if you use dynamic phase adjustment. If you're trying to capture data without using dynamic phase adjustment, I think the tools are correct in limiting you to about 10 MSPS.
08-24-2015 08:08 AM
Thanks very much for your response.
By "adjust clock phase" do you mean to sync individual bits or to sync entire frames (12 bits of data) ?
I use the pattern mode of the AFE to train the link (both for the bits alignement 010101 010101 and for the sample frame 00000 111111). I even use a custom non-pattern 110001 111100, and this works fine below 7MSPS. Above that the training fails and it bitslips indefinately. I'm using an Opal Kelly XEM6010 and the AFE on a connected custom board for development.
How could I capture with dynamic phase adjustment? I must have missed this part in my reading.