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4,456 Views
Registered: ‎03-28-2013

Spartan 6 LX25 MCB timing fails on component switching limit

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Hello all,

I'm working on a design which uses an XC6SLX25-2CSG324I connected to a DDR3 1Gb memory (MT41J64M16JT-15E) on bank 3.

The design is an ISE 14.5 design with an xps subsystem containing a uBlaze and an AXI-ddr memory controller (1.06a).

 

The DDR controller is connected to a clock-generator component which on clock 0 and 1 outputs a frequency of 629 Mhz.

 

The design is working fine, any memory test I run passes without problems, but I get a component switching limit failure:

 

Timing constraint: TS_XpsSoCInst_clock_generator_0_CLKOUT1 = PERIOD TIMEGRP "XpsSoCInst_clock_generator_0_CLKOUT1" TS_iSysClk / 24 PHASE 0.794728604 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
1 timing error detected. (1 component switching limit error)
Minimum period is 1.599ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_XpsSoCInst_clock_generator_0_CLKOUT1 = PERIOD TIMEGRP
"XpsSoCInst_clock_generator_0_CLKOUT1" TS_iSysClk / 24 PHASE
0.794728604 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: -0.010ns (period - min period limit)
Period: 1.589ns
Min period limit: 1.599ns (625.391MHz) (Tmcbcper_PLLCLK)
Physical resource: XpsSoCInst/axi_s6_ddrx_0/axi_s6_ddrx_0/mcb_ui_top_0/mcb_raw_wrapper_inst/samc_0/PLLCLK1
Logical resource: XpsSoCInst/axi_s6_ddrx_0/axi_s6_ddrx_0/mcb_ui_top_0/mcb_raw_wrapper_inst/samc_0/PLLCLK1
Location pin: MCB_X0Y1.PLLCLK1
Clock network: XpsSoCInst/axi_s6_ddrx_0/sysclk_2x_180_bufpll_o

 

Now I was under the impression that a LX25 speedgrade 2 device could achieve a frequency of 667MHz for the memory controller (see DS162 Table 25).

 

A 'normal' timing failure I could understand, but a component switching limit failure seems odd.

 

I'm a bit lost and could use some advice/pointers on where to start digging.

 

Any ideas?

 

 

Best regards,

 

 

Olaf

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Highlighted
4,787 Views
Registered: ‎03-28-2013

Ok, never mind, I've found the answer..

 

In my ucf there was the line:

CONFIG MCB_PERFORMANCE=STANDARD;

 

which should be:

CONFIG MCB_PERFORMANCE=EXTENDED; 

Eventhough for DDR3 it shouldn't matter (for DDR2 it does), the timing analyzer apparently checks against a different timing model for the standard setting.

 

 

Best regards,

 

Olaf

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2 Replies
Highlighted
4,788 Views
Registered: ‎03-28-2013

Ok, never mind, I've found the answer..

 

In my ucf there was the line:

CONFIG MCB_PERFORMANCE=STANDARD;

 

which should be:

CONFIG MCB_PERFORMANCE=EXTENDED; 

Eventhough for DDR3 it shouldn't matter (for DDR2 it does), the timing analyzer apparently checks against a different timing model for the standard setting.

 

 

Best regards,

 

Olaf

View solution in original post

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Professor
Professor
4,440 Views
Registered: ‎08-14-2007

Thanks for posting the solution.  You can mark your second post as a solution to help people searching for the answer to the same problem.  Just to clarify one point, was the line you changed part of the automatically generated UCF from the MIG core?

-- Gabor
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