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Adventurer
Adventurer
4,951 Views
Registered: ‎04-22-2008

Spartan 6 Layout Questions

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Hey all, I'm in the process of putting together a Spartan 6 design, and I've got two questions regarding PCB layout issues.

 

First off, does anyone know how large an NSMD pad has to be for the FG484 package?  I'd love to be able to get away with 0.5mm; anything larger doesn't let you route a trace between balls with 6 mil trace/space.

 

Secondly, I'm using one of the memory interfaces to connect over to a single 16 bit wide DDR2 DRAM.  The traces are crossing over one another every which way, and threating to really make a mess of the routing in that area.  It seems to me, reading through the datasheets, that

  1. Any of the pins DQ(15:8) can be swapped with one another
  2. Any of the pins DQ(7:0) can be swapped with one another
  3. Any of the pins BA(2:0) can be swapped with one another
  4. Everything else has to go where it was meant to

If that's really the case, I can disentangle things beautifully.  Anyone know if I can?

 

Thanks,

Rob

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-23-2007

Page 85 of http://www.xilinx.com/support/documentation/user_guides/ug388.pdf makes it clear that 1 and 2 are okay, and of course #4 in your list is okay.  I do not believe you can swap the BA bits because they are used for the mode register address and swapping them would cause the controller to not initialize the memory properly.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-23-2007

Page 85 of http://www.xilinx.com/support/documentation/user_guides/ug388.pdf makes it clear that 1 and 2 are okay, and of course #4 in your list is okay.  I do not believe you can swap the BA bits because they are used for the mode register address and swapping them would cause the controller to not initialize the memory properly.

 

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Adventurer
Adventurer
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Registered: ‎04-22-2008
Thanks a lot.  I knew I had seen something somewhere (page 83 if you're still on v1.0 of UG388), but wasn't able to find it when I'd been looking.
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