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Scholar joelby
Scholar
5,751 Views
Registered: ‎10-05-2010

Spartan 6 SelectIO Interface Wizard synthesis problems

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Hi all!
It seems like ISERDES2 is pretty poopular on the Spartan 6, but has anyone had any luck with the SelectIO wizard? I'm trying to connect a four channel ADC with eight LVDS pairs to an XC6SLX45-CSG324C and am having trouble getting a skeleton design to map. Some other parameters - DDR, differential clock supplied by the ADC at 50 MHz, serialization factor 8, BITSLIP supplied by ADC's frame signal, phase detector.
When mapping, I get multiple errors similar to:

 

 

The BUFIO instance <adc_deser/bufio2_inst> needs to have all

 

 

of its IOB loads placed into its same half IO bank. However, the user has

 

 

locked it to site <BUFIO2_X3Y6>, and locked its IOB load <ltc_in_p<3>> to

 

 

site <PAD209>, which is in a different half IO bank. Please check

 

 

user-specified LOCATION constraints and make sure they do not violate this

 

 

rule.

 

 

I haven't specified any location constraints - does the Coregen bury location constraints somewhere obscure? It's created an adc_deser.ucf, but this only contains a copyright notice. I couldn't find any document that stated which IO bank everything was in, but eyeballing the FPGA Editor indicates that PAD209 is at least within spitting distance of BUFIO2_X3Y6.
If I disable the input data routing delay, I get just one error,

 

 

ERROR:Place:1318 - User has over-constrained component

 

 

adc_deser/bufio2_inv_inst. There are no placeable sites that satisfy the user

 

 

constraints. Please review the user constraints on the driver component and

 

 

the load components of adc_deser/bufio2_inv_inst.

 

 

   
I've checked that Coregen is targeting the same chip as ISE, deleted all of the Coregen-generated files and upgraded from 12.2 to 12.4, and tried using the wizard with only two of the pairs instead of all eight with no luck. Am I missing something simple?
Thanks everyone!
Joel

 

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Moderator
Moderator
7,084 Views
Registered: ‎07-30-2007

Re: Spartan 6 SelectIO Interface Wizard synthesis problems

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I believe the wizard is assuming that the design will be contained in a half bank and doesn't instantiate enough BUFIO2's to make the connections needed.  I will look into making the wizard handle this.  In any case the code examples in XAPP1064 should work for you.

 

Roy

 

 




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4 Replies
Moderator
Moderator
7,085 Views
Registered: ‎07-30-2007

Re: Spartan 6 SelectIO Interface Wizard synthesis problems

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I believe the wizard is assuming that the design will be contained in a half bank and doesn't instantiate enough BUFIO2's to make the connections needed.  I will look into making the wizard handle this.  In any case the code examples in XAPP1064 should work for you.

 

Roy

 

 




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Don't forget to reply, kudo, and accept as solution
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Scholar joelby
Scholar
5,699 Views
Registered: ‎10-05-2010

Re: Spartan 6 SelectIO Interface Wizard synthesis problems

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Thanks Roy. I figured that there might be some quirk and am in the process of implementing something based on XAPP1064. I'm happier going through the code and knowing what it all does anyway!

 

Joel

 

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Scholar joelby
Scholar
5,674 Views
Registered: ‎10-05-2010

Re: Spartan 6 SelectIO Interface Wizard synthesis problems

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Predictably, I've run into the same problem with XAPP1064. What were you thinking about doing to BUFIO2s to span the half banks?

 

I'm using code based on serdes_1_to_n_clk_ddr_s8_diff and have tried duplicating the BUFIO2_2CLK and BUFIO2 and feeding the ISERDESes associated with each half bank with their own, which caused the error:

 

 

ERROR:Place:1073 - Placer was unable to create RPM[BUFIO_RPMs] for the component
   ltc_deser/inst_clkin/bufio2_inst_b of type BUFIO for the following reason.
   The reason for this issue:
   The structured logic has to be merged with another RPM which causes a
   placement violation for component ltc_deser/inst_clkin/bufio2_inst_a. The
   following components are part of this structure:
      BUFIO   ltc_deser/inst_clkin/bufio2_inst_b
      IODELAY   ltc_deser/inst_clkin/loop1[0].iodelay_s

 This looks like it didn't want to share the IODELAYs. If I also duplicate the two IODELAY2s, the error is:

 

 

 

Phase 1.1  Initial Placement Analysis
ERROR:Place:1073 - Placer was unable to create RPM[IOBM_Alignment_RPMs] for the
   component ltc_clk_n of type IOB for the following reason.
   The reason for this issue:
   This structured logic should be aligned in a specific way on the CLB grid. In
   this case, the logic is locked to a position that has not this specific
   alignment. The problem was found with IOB ltc_clk_n that is locked to site
   PAD208. The following components are part of this structure:
      IOB   ltc_clk_n

All signs seems to point to the fact that I should be using a PLL multiplying the input clock by two (for DDR) and BUFPLL instead. I had a fiddle and this (data reception case 2 in XAPP1064) appears to be a case that the wizard doesn't handle. Anyway, I'll try that!

 

Thanks,

Joel

 

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Visitor bennijudge1
Visitor
822 Views
Registered: ‎05-13-2018

Re: Spartan 6 SelectIO Interface Wizard synthesis problems

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Hello everybody,

 

i ran into the same problem and would like to ask if anybody has found a solution for the mapping failure.

 

Best Regards,

Benni

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