Hallo,
UG382 states: "Each GTP reference clock is associated with a BUFIO2. This can affect the global clock pins located in Bank 0 or Bank 2".
UG386 nicely documents how to route the various GTP clocks over BUFIO2s. But I could not find a table or figure which descibes exactly how GPTs and BUFIO2s are connected. I'm looking for the complenent of Figure 1-3 and 1-4 in UG383 where the connection betwenn GCLK pins, BUFIO2s and BUFGMUXs is documented.
We have an application where we have source synchronous data capture and GTP usage with 'RX/TX bypass' in bank 0 and it is important to understand all the regional and global clock constaints.
Any pointer to the location of this documentation is much appreciated.
