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Visitor
Visitor
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Registered: ‎09-08-2015

[Spartan 6 - XC6SLX45] Unable to Clock forwarding to external port using PLL_ADV primitive

Hello,

 

I'm using Spartan 6 and trying to forward clock to external pin.

I used PLL_ADV primitve and ODDR2 buffer to do so.

I completed 1)sythesis 2)implement design and 3)generate programming file without any errors.

 

However, I couldn't have any signal coming out from the pin that I designated for clock output pin when I proved this pin with oscilloscope.

I attatched source code(.v), ucf file(for mapping I/O port to HDL module) and RTL schematic below.

 

Currently, I don't have any clue about solving this problem.

To me, I should be workgin properly.

 

I'm novice in FPGA field.

Can anyone help me?

 

I'd appreciate it in advance.

 

 

 

1. My FPGA device : Opal kelly XEM6310

    - LVDS external clock source(100MHz) is connected to FPGA's clock input  terminal (Y11, AB11)

    - I used BUFGDS to take differential input source and to feed this to clock input port of PLL_ADV premitive.

 

2. Source code (.v)

 

`timescale 1ns / 1ps

module clk_core(
    input sys_clk_p,
    input sys_clk_n,
  input RST_N,
    output sys_clk_out
    );


wire sys_clk_ibufg;
wire clk_1M;
wire clk_1M_bufg;

wire clkfbout_clkfbin;
wire RST_internal;

 

IBUFGDS u_ibufg_sys_clk (.I(sys_clk_p), .IB(sys_clk_n), .O(sys_clk_ibufg));
BUFG u_clock1M (.I(clk_1M), .O(clk_1M_bufg));


PLL_ADV # (
  .BANDWIDTH          ("OPTIMIZED"),
  .CLKIN1_PERIOD      (10),
  .CLKIN2_PERIOD      (10),
  .CLKOUT0_DIVIDE     (100),
  .CLKOUT1_DIVIDE     (),
  .CLKOUT2_DIVIDE     (),
  .CLKOUT3_DIVIDE     (),
  .CLKOUT4_DIVIDE     (),
  .CLKOUT5_DIVIDE     (),
  .CLKOUT0_PHASE      (0.000),
  .CLKOUT1_PHASE      (180.000),
  .CLKOUT2_PHASE      (0.000),
  .CLKOUT3_PHASE      (0.000),
  .CLKOUT4_PHASE      (0.000),
  .CLKOUT5_PHASE      (0.000),
  .CLKOUT0_DUTY_CYCLE (0.500),
  .CLKOUT1_DUTY_CYCLE (0.500),
  .CLKOUT2_DUTY_CYCLE (0.500),
  .CLKOUT3_DUTY_CYCLE (0.500),
  .CLKOUT4_DUTY_CYCLE (0.500),
  .CLKOUT5_DUTY_CYCLE (0.500),
  .SIM_DEVICE         ("SPARTAN6"),
  .COMPENSATION       ("INTERNAL"),
  .DIVCLK_DIVIDE      (1),
  .CLKFBOUT_MULT      (5),
  .CLKFBOUT_PHASE     (0.0),
  .REF_JITTER         (0.005000)
 ) u_pll_adv (
  .CLKFBIN     (clkfbout_clkfbin),
  .CLKINSEL    (1'b1),
  .CLKIN1      (sys_clk_ibufg),
  .CLKIN2      (1'b0),
  .DADDR       (5'b0),
  .DCLK        (1'b0),
  .DEN         (1'b0),
  .DI          (16'b0),
  .DWE         (1'b0),
  .REL         (1'b0),
  .RST         (RST_internal),
  .CLKFBDCM    (),
  .CLKFBOUT    (clkfbout_clkfbin),
  .CLKOUTDCM0  (),
  .CLKOUTDCM1  (),
  .CLKOUTDCM2  (),
  .CLKOUTDCM3  (),
  .CLKOUTDCM4  (),
  .CLKOUTDCM5  (),
  .CLKOUT0     (clk_1M),
  .CLKOUT1     (),
  .CLKOUT2     (),
  .CLKOUT3     (),
  .CLKOUT4     (),
  .CLKOUT5     (),
  .DO          (),
  .DRDY        (),
  .LOCKED      ()
 );

assign RST_internal = ~RST_N;


// ODDR2: Output Double Data Rate Output Register with Set, Reset
// and Clock Enable.
// Spartan-6
// Xilinx HDL Libraries Guide, version 13.1
 ODDR2 #(
  .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
  .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
  .SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
 ) ODDR2_inst (
  .Q(sys_clk_out), // 1-bit DDR output data
  .C0(clk_1M_bufg), // 1-bit clock input
  .C1(~clk_1M_bufg), // 1-bit clock input
  .CE(1'b1), // 1-bit clock enable input
  .D0(1'b0), // 1-bit data input (associated with C0)
  .D1(1'b1), // 1-bit data input (associated with C1)
  .R(1'b0), // 1-bit reset input
  .S(1'b0) // 1-bit set input
 );
// End of ODDR2_inst instantiation

 

endmodule

 

 

 

 

3. UCF code (.ucf)

 

NET "sys_clk_p"      LOC=Y11   | IOSTANDARD=LVDS_25;
NET "sys_clk_n"      LOC=AB11  | IOSTANDARD=LVDS_25;

NET "sys_clk_p" TNM_NET = "okSysClk";
TIMESPEC "TS_okSysClk" = PERIOD "okSysClk" 10 ns HIGH 50%;


NET "sys_clk_out" LOC="K22" | IOSTANDARD=LVCMOS33; # JP2-62
NET "RST_N" LOC="G22" | IOSTANDARD=LVCMOS33; # JP2-66

 

 

 

4. RTL schematic

 

For RESET (toggling RST_N), I used manual switch on my own PCB to make the RST_N logical 0.

 

clock forwarding schematic.png

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7 Replies
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Moderator
Moderator
8,510 Views
Registered: ‎01-15-2008

can you check if the reset pulse is provided to the pll from your board?

 

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Community Manager
Community Manager
8,505 Views
Registered: ‎07-23-2012

Can you please monitor LOCKED status either in chipscope or connect it to a LED.
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Visitor
Visitor
8,491 Views
Registered: ‎09-08-2015

Thank you for helping me first. :D

Yes, I can manually toggle a switch that can provide reset pulse to PLL reset input.
When switch is on, reset is done.
when switch is off, no reset takes place.
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Visitor
Visitor
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Registered: ‎09-08-2015

Thank you for kind reply.
I set some other pin in both .v code and ucf source so as to monitoring LOCKED status.

------------------------added line in .ucf file-------------
NET "LOCK" LOC="E22" | IOSTANDARD=LVCMOS33; # JP2-70
-----------------------------------------------------------------

LOCKED stays at logical 0 and no transition happened.

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Community Manager
Community Manager
8,484 Views
Registered: ‎07-23-2012

It means that either the clock provided to PLL is not valid (or not provided at all) or the PLL is in reset state.

Please do one the following things-

1. Drive a flipflop with the input clock to the PLL and see if you were able to see any output on FF either in chipscope or on status LEDs. This will prove that the input clock to PLL is stable.

2. Drive the reset through VIO core to make sure that the reset was correctly provided and it is not an issue with the DIP switch on board.
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Visitor
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Registered: ‎09-08-2015

Smarell,

 

Thank you for keep advising me. :D

 

To respond your comment,

 

1) Since I don't have chipscope, I need to go for status LEDs trial.

    What I checked with LVDS clock source was waveform of single output coming out from it.

    It looks like below in captured image.

    Since I/O group of GCLK input pin is LVDS_25, the waveform seems to be a  in range of spec.

   However, what i'm not sure is that it's shape is ok for clock buffer to take it and work properly.

   it is not pulse and it's more of sine wave.

   LVDS clock generator output.jpg

 

 

2) I can't follow your suggetion here.

    How can I use VIO core with Spartan 6?

    If I want to use VIO core, then shouldn't I purchase chipscope, should I?

    I'm a beginner. So can you please let me know how can I check it reset signal operates properly with VIO core?

 

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Moderator
Moderator
8,463 Views
Registered: ‎02-16-2010

chipscope does not require license.

From the code I find reset input to the PLL looks to be active-LOW. If not please correct the following code.
assign RST_internal = ~RST_N;

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