cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
rlingemann
Visitor
Visitor
148 Views
Registered: ‎02-11-2019

Spartan 6 bufpll problem

I am trying to generate a LVDS output in a Spartan 6 design. I am using a PLL to generate both clocks and a BUFPLL to distribute them to the SERDESs, folled by a LVDS33 driver. The code is appended below. I get the message "User has over-constrained component BPclk350. There are no placeable sites ...". Can you tell me what's wrong.

Ron

-- PLL_LVDS : Base Mixed Mode Clock Manager for LVDS frequencies of 50 and 350 MHz
PLL_LVDS_inst : PLL_BASE
generic map (
COMPENSATION => "SYSTEM_SYNCHRONOUS",
BANDWIDTH => "OPTIMIZED",
CLKOUT0_DIVIDE => 3, -- 350 MHz
CLKOUT1_DIVIDE => 21, -- 50 MHz
CLKOUT2_DIVIDE => 21, -- 50 MHz 180 deg
CLKOUT3_DIVIDE => 8, -- 131.25 MHz
CLKOUT4_DIVIDE => 4, -- 262.5 MHz
CLKOUT5_DIVIDE => 42, -- 25 MHz
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 180.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT0_DUTY_CYCLE => 0.50,
CLKOUT1_DUTY_CYCLE => 0.50,
CLKOUT2_DUTY_CYCLE => 0.50,
CLKOUT3_DUTY_CYCLE => 0.50,
CLKOUT4_DUTY_CYCLE => 0.50,
CLKOUT5_DUTY_CYCLE => 0.50,
CLKFBOUT_MULT => 20, -- 350 MHz
DIVCLK_DIVIDE => 1,
CLKFBOUT_PHASE => 0.0,
CLKIN_PERIOD => 20.000,
CLK_FEEDBACK => "CLKFBOUT"
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKIN => SysClk_O,
CLKFBIN => CLKFBOUT,
CLKOUT0 => CLK350_B, -- 350MHz out
CLKOUT1 => nCLK50, -- 50 MHz out, inverted
CLKOUT2 => CLK50, -- 50 MHz out
CLKFBOUT => CLKFBOUT,
LOCKED => LOCKLVDS,
RST => RST -- 1-bit input: Reset
);

Bclkin_inst : BUFG -- 50 MHz clock distribution
port map(I => SysClk, O => SysClk_O);

Bclk50_inst : BUFG
port map(I => Clk50, O => Clk50_O);

BstbOut_inst : BUFG
port map(I => Clk350_B, O => Clk350);

BPclk350 : BUFPLL -- 350 MHz clock distribution
-- generic map(DIVIDE => 7, ENABLE_SYNC => FALSE)
port map(PLLIN => Clk350, IOCLK => Clk350_O, GCLK => Clk50_O, LOCKED => LOCKLVDS, LOCK => LOCK, SERDESSTROBE => LvdsCe);

OclkTest_inst : OBUF
port map(I => ClkDivider(0), O => ClkTest);

LVDSCx_inst : OBUFDS
generic map (slew => "FAST")
port map (I => LVDSc, O => LcdCp, OB => LcdCn);

--LVDSD3x_inst : OBUFDS
--generic map (IOSTANDARD => "LVDS_25", slew => "FAST")
--port map (O => LcdDP3, OB => LcdDN3, I => LVDSD3);
--
--LVDSD2x_inst : OBUFDS
--generic map (IOSTANDARD => "LVDS_25", slew => "FAST")
--port map (O => LcdDP2, OB => LcdDN2, I => LVDSD2);
--
--LVDSD1x_inst : OBUFDS
--generic map (IOSTANDARD => "LVDS_25", slew => "FAST")
--port map (O => LcdDP1, OB => LcdDN1, I => LVDSD1);
--
--LVDSD0x_inst : OBUFDS
--generic map (IOSTANDARD => "LVDS_25", slew => "FAST")
--port map (O => LcdDp0, OB => LcdDn0, I => LVDSD0);

-- OSERDESE2: Output SERial/DESerializer with bitslip
-- Clock bit master, 3 MSBs
LVDSCH_inst : OSERDES2
generic map (
DATA_RATE_OQ => "SDR", -- DDR, SDR
DATA_RATE_OT => "SDR",
DATA_WIDTH => 7, -- Parallel data width
SERDES_MODE => "MASTER", -- MASTER, SLAVE
OUTPUT_MODE => "SINGLE_ENDED"
)
port map (
OQ => LVDSc, -- 1-bit output: Data path output
-- SHIFOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
TQ => TQ, -- 1-bit output: 3-state control
CLK0 => Clk350_O, -- 1-bit input: High speed clock
Clk1 => '1',
CLKDIV => Clk50_O, -- 1-bit input: Divided clock
-- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
D1 => '1',
D2 => '0',
D3 => '0',
D4 => '0',
IOCE => LvdsCe,
OCE => '1', -- 1-bit input: Output data clock enable
RST => RST, -- 1-bit input: Reset
-- SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
SHIFTIN1 => '1',
SHIFTIN2 => '1',
SHIFTIN3 => sm_d,
SHIFTIN4 => sm_t,
SHIFTOUT1 => ms_d,
SHIFTOUT2 => ms_t,
-- T1 - T4: 1-bit (each) input: Parallel 3-state inputs
T1 => '1',
T2 => '1',
T3 => '1',
T4 => '1',
TRAIN => '0',
TCE => '1' -- 1-bit input: 3-state clock enable
);

-- OSERDESE2: Output SERial/DESerializer with bitslip
-- Clock bit slave, 4 LSBs
LVDSCL_inst : OSERDES2
generic map (
DATA_RATE_OQ => "SDR", -- DDR, SDR
DATA_RATE_OT => "SDR",
DATA_WIDTH => 7, -- Parallel data width
SERDES_MODE => "SLAVE", -- MASTER, SLAVE
OUTPUT_MODE => "SINGLE_ENDED"
)
port map (
OQ => OQ, -- 1-bit output: Data path output
-- SHIFOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
TQ => TQ, -- 1-bit output: 3-state control
CLK0 => Clk350_O, -- 1-bit input: High speed clock
Clk1 => '1',
CLKDIV => Clk50_O, -- 1-bit input: Divided clock
-- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
D1 => '0',
D2 => '0',
D3 => '1',
D4 => '1',
IOCE => LvdsCe,
OCE => '1', -- 1-bit input: Output data clock enable
RST => RST, -- 1-bit input: Reset
-- SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
SHIFTIN1 => ms_d,
SHIFTIN2 => ms_t,
SHIFTIN3 => '1',
SHIFTIN4 => '1',
SHIFTOUT1 => sm_d,
SHIFTOUT2 => sm_t,
-- T1 - T4: 1-bit (each) input: Parallel 3-state inputs
T1 => '1',
T2 => '1',
T3 => '1',
T4 => '1',
TRAIN => '0',
TCE => '1' -- 1-bit input: 3-state clock enable
);

 

# Clocks
NET "SysClk" LOC = "A10" | IOSTANDARD = LVCMOS33; # Input clock - 50 MHz
# NET "Clk50" LOC = "F13" | IOSTANDARD = LVCMOS33; # pin A7-21
# NET "Clk350_o" LOC = "F14" | IOSTANDARD = LVCMOS33; # pin A7-22
# PIN "BUFG2_inst.O" CLOCK_DEDICATED_ROUTE = FALSE;
# PIN "Bclk50_inst.O" CLOCK_DEDICATED_ROUTE = FALSE;
# PIN "BUFGIN_inst.O" CLOCK_DEDICATED_ROUTE = FALSE;
# PIN "BUFG_inst.GCLK" CLOCK_DEDICATED_ROUTE = FALSE;
# PIN "BstbOut_inst.O" CLOCK_DEDICATED_ROUTE = FALSE;
# PIN "Bclkin_inst.O" CLOCK_DEDICATED_ROUTE = FALSE;

# LVDS output
#net "LcdDP0" LOC = "D6" | IOSTANDARD = LVDS_33; # pin A8-39
#net "LcdDN0" LOC = "C6" | IOSTANDARD = LVDS_33; # pin A8-38
#net "LcdDP1" LOC = "F7" | IOSTANDARD = LVDS_33; # pin A8-37
#net "LcdDN1" LOC = "E6" | IOSTANDARD = LVDS_33; # pin A8-36
#net "LcdDP2" LOC = "D8" | IOSTANDARD = LVDS_33; # pin A8-34
#net "LcdDN2" LOC = "C8" | IOSTANDARD = LVDS_33; # pin A8-33
#net "LcdDP3" LOC = "F10" | IOSTANDARD = LVDS_33; # pin A8-30
#net "LcdDN3" LOC = "E11" | IOSTANDARD = LVDS_33; # pin A8-29
net "LcdCP" LOC = "F9" | IOSTANDARD = LVDS_33;# | DIFF_TERM = 100; # pin A8-31
net "LcdCN" LOC = "D9" | IOSTANDARD = LVDS_33; # pin A8-32

0 Kudos
0 Replies