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Visitor
Visitor
5,040 Views
Registered: ‎06-10-2014

Spartan 6 configuration times

Hello,

 

I have been reading the user guide (ug380.pdf) and "DC and Switching Characteristics" (ds162.pdf) to collect information about the Configuration Sequence and the time that it needs. Chapter 5  of the userguide (ug380,page 78) describes this Sequence in 8 Steps for any Configuration Mode.

 

Since my application is time-critical, I need to calculate the configuration time in worstcase scenarios for Master Serial/SPI Mode (M[1:0] = 01) and Slave SelectMAP (M[1:0] = 10) exactly (2ms exact). I have been able to do so for Step1 (Device Power-Up) and Step6 (Load Configuration Data). 

 

I cant find timing information about the other steps in this documentation, particularly the last step (Step8: Startup Sequence) seems to vary alot among different Designs that are loaded on the FPGA.

 

Thanks

Human

 

 

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Community Manager
Community Manager
5,037 Views
Registered: ‎07-23-2012

Re: Spartan 6 configuration times

Hi Human,

As mentioned in UG380, under Startup section, the startup time would depend on time take for DCM/PLL to LOCK. Once this is done, the time for the completion of startup is 7 cycles as shown in Figure 5-12 of http://www.xilinx.com/support/documentation/user_guides/ug380.pdf

The PLL lock time totally depends on your board and the quality of the input clock.

Regards,
Krishna
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