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Contributor
Contributor
3,563 Views
Registered: ‎04-25-2013

Spartan 6 high impedance warning

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Hi!

 

I keep getting a warning from Xilinx ISE 14.7 when programming my Spartan 6 LX9 device.
I get the warning

WARNING:Xst:2041 - Unit test: 1 internal tristate is replaced by logic (pull-up yes): N2.

even though, the signal N2 does not exists and that the tristate-signal output is directly connected to an output pin of the Spartan 6 device. I understand from this answer (https://forums.xilinx.com/t5/Welcome-Join/Problem-with-high-impedance-output-signals/m-p/325043/highlight/true#M4452) that high impedance is allowed for signals that are directly connected to output pins.

 

How should I understand the warning and/or can you give me an example of how I should code to avoid it?

 
My code :

entity test is
	Generic(
		DEFAULT_DECAY	: STD_ULOGIC := 'Z';
		RESET_VALUE	: STD_ULOGIC := '1'
	);
	Port(
		RST		: in	STD_ULOGIC;
		CLK		: in	STD_ULOGIC;
		
		output_select	: in	STD_ULOGIC_VECTOR (1 downto 0);		
		
		en_x		: in	STD_ULOGIC;
		output		: out	STD_ULOGIC
	);
end test;

architecture Behavioral of test is
signal use_high_Z : std_ulogic;
begin

use_high_Z <= '1' when (output_select = "11" OR output_select = "00") else '0';

output_generator : process (CLK, RST, en_x)
begin
if rising_edge(CLK) then
	if(RST = RESET_VALUE) then
		output <= DEFAULT_DECAY;
	else
		if(en_x = '1') then
			if(use_high_Z = '1') then
				output <= 'Z';
			else
				output <= output_select(1);
			end if;
		end if;
	end if;
end if;
end process;

end Behavioral;

 

Thank you!

 

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1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
6,482 Views
Registered: ‎09-05-2007

Re: Spartan 6 high impedance warning

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My recommendation is that you isolate the definition of the tri-state behaviour from that of the logical functions that drive it.

 

At the top level of your design and outside of any clocked process define the tri-state output. For example…

 

output_pin <= drive_value when drive_output = ‘1’ else ‘Z’

 

Then create logical functions (inside or outside of clocked processes) that define internal signals called ‘drive_value’ and ‘drive_output’.

 

I think the issue could relate to the way that your nested if-then-else code doesn’t fully define every outcome (i.e. assumes what would happen in some situations) and I don’t feel comfortable that the ‘Z’ state could result from an asynchronous reset, synchronous event or feedback of ‘Z’ (which is impossible).

 

In practice, this is about defining the behaviour of the output buffer which is a combinatorial element.

Ken Chapman
Principal Engineer, Xilinx UK
5 Replies
Xilinx Employee
Xilinx Employee
3,502 Views
Registered: ‎09-05-2007

Re: Spartan 6 high impedance warning

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I think it may be because you are using the type 'STD_ULOGIC' rather than 'std_logic'.

Ken Chapman
Principal Engineer, Xilinx UK
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Contributor
Contributor
3,479 Views
Registered: ‎04-25-2013

Re: Spartan 6 high impedance warning

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Thank you for your response, Ken Chapman.

 

I have tested your suggestion by replacing all STD_ULOGIC with STD_LOGIC. Unfortunately this changed nothing and I get the same warning.

I would ignore this warning if I understood why it appears, but I am afraid of ignoring somthing that I do not understand completely. Especially when it is not just a school exercise, but a real product.

 

I took a longshot and tested the above design with a constraint file attached to make it even more clear to ISE that the output is connected to a pin, but the warning remains.

 

I appreciate any suggestions.

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Xilinx Employee
Xilinx Employee
6,483 Views
Registered: ‎09-05-2007

Re: Spartan 6 high impedance warning

Jump to solution

My recommendation is that you isolate the definition of the tri-state behaviour from that of the logical functions that drive it.

 

At the top level of your design and outside of any clocked process define the tri-state output. For example…

 

output_pin <= drive_value when drive_output = ‘1’ else ‘Z’

 

Then create logical functions (inside or outside of clocked processes) that define internal signals called ‘drive_value’ and ‘drive_output’.

 

I think the issue could relate to the way that your nested if-then-else code doesn’t fully define every outcome (i.e. assumes what would happen in some situations) and I don’t feel comfortable that the ‘Z’ state could result from an asynchronous reset, synchronous event or feedback of ‘Z’ (which is impossible).

 

In practice, this is about defining the behaviour of the output buffer which is a combinatorial element.

Ken Chapman
Principal Engineer, Xilinx UK
Contributor
Contributor
3,434 Views
Registered: ‎04-25-2013

Re: Spartan 6 high impedance warning

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Thank you - that was the issue!

 

For future people who may encounter the same issue, I present a way to implement the origianl code without warnings:

 

entity test is
	Generic(
		DEFAULT_DECAY	: STD_LOGIC := 'Z';
		RESET_VALUE	: STD_LOGIC := '1'
	);
	Port(
		RST		: in	STD_LOGIC;
		CLK		: in	STD_LOGIC;
		
		output_select	: in	STD_LOGIC_VECTOR (1 downto 0); -- 00->'Z', 01->'0', 10->'1', 11->'Z'
		
		en_x		: in	STD_LOGIC;
		output		: out	STD_LOGIC
	);
end test;

architecture Behavioral of test is
signal use_high_Z : STD_LOGIC;
signal output_state : std_ulogic;	-- '0' is value, '1' is high impedance
signal output_value : std_ulogic;	-- value of output, if output_state is '0'
begin

output <= '0' when (output_value = '0' AND output_state = '0') else 
'1' when (output_value = '1' AND output_state = '0') else
'Z'; use_high_Z <= '1' when (output_select = "11" OR output_select = "00") else '0'; output_generator : process (CLK, RST, en_x) begin if rising_edge(CLK) then if(RST = RESET_VALUE) then if(DEFAULT_DECAY = 'Z') then output_state <= '1'; output_value <= '0'; else output_state <= '0'; output_value <= DEFAULT_DECAY; end if; else if(en_x = '1') then output_state <= use_high_Z; output_value <= output_select(1); end if; end if; end if; end process; end Behavioral;
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Xilinx Employee
Xilinx Employee
3,424 Views
Registered: ‎09-05-2007

Re: Spartan 6 high impedance warning

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Good to hear you are making progress. A couple of things about your latest code...

 

'output_value' is an internal signal so in practical terms it can only have the values '0' and '1'. You cannot drive an internal signal to 'Z' but you have the line 'output_value <= DEFAULT_DECAY' in which the default state of  'DEFAULT_DECAY' has been earlier defined to be 'Z'. As it stands, this code will only make sense if the  'DEFAULT_DECAY' generic is being set to '0' or '1' in the instantiation of this entity at the next higher level of your design.

 

Since you have defined a nice synchronous clocked process only the 'CLK' needs to be in the process sensitivity list.

 

Ken Chapman
Principal Engineer, Xilinx UK
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