09-10-2014 08:11 AM
tool: Xilinx ISE v14.7
I am using the follow command line to create readback files:
bitgen -w -b -g Readback -l xdesign.ncd xdesign.bit
The the logic allocation file, xdesign.ll, created using the above command line is basically empty. It only contains
header info. See the contents of the xdesign.ll file below.
Anybody have any idea what I am doing wrong?
; Created by bitgen P.20131013 at Wed Sep 10 09:58:40 2014
; Bit lines have the following form:
; <offset> <frame address> <frame offset> <information>
; <information> may be zero or more <kw>=<value> pairs
; Block=<blockname specifies the block associated with this
; memory cell.
; Latch=<name> specifies the latch associated with this memory cell.
; Net=<netname> specifies the user net associated with this
; memory cell.
; COMPARE=[YES | NO] specifies whether or not it is appropriate
; to compare this bit position between a
; "program" and a "readback" bitstream.
; If not present the default is NO.
; Ram=<ram id>:<bit> This is used in cases where a CLB function
; Rom=<ram id>:<bit> generator is used as RAM (or ROM). <Ram id>
; will be either 'F', 'G', or 'M', indicating
; that it is part of a single F or G function
; generator used as RAM, or as a single RAM
; (or ROM) built from both F and G. <Bit> is
; a decimal number.
; Info lines have the following form:
; Info <name>=<value> specifies a bit associated with the LCA
; configuration options, and the value of
; that bit. The names of these bits may have
; special meaning to software reading the .ll file.
08-04-2017 10:56 AM
The same issue apparently still exists three years on: using ISE 14.7, a simple design with a block RAM *does* include that in the logic allocation file, but a simple design including a number of FDRE instances is just as described below - no info at all about the FFs.
Are extra options to Bitgen required? I've checked the latest version of the command-line reference, and could find no further info about this; and the BlockRAM design generated the required info without any special magic. As it stands, this aspect of the tool's behavior appears seriously broken at least for Spartan 6.
08-12-2017 10:34 AM
Think I found out the answer to my own question: the capability of Configuration Readback varies among Xilinx device families, and Spartan-6 is among those that don't support it.
Request to Xilinx, if anyone reads this: please consider improving ug380, Ch6 "Readback and Configuration Verification", first paragraph, to make clear that config read back can retrieve the current values only for cells of specific types.
In the current version of the doc v2.10 (Mar 31, 2017) this para says: "During readback, the user reads back all configuration memory cells, including the current values on all user memory elements (LUT RAM, SRL16, and Block RAM)." I took the phrase 'user memory elements' to include FFs, such as instances of FDRE, and clearly I'm not the only one to do so (web search quickly turns up others asking the same question, besides the original posting here). Please delete that phrase, and instead just state explicitly that LUT RAM, SRL16, and Block RAM are in fact the *only* cell types whose values are available in Spartan 6 config readback; also state explicitly that the state of FF cell types can NOT be accessed (FDRE etc.)