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Professor
Professor
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Registered: ‎08-14-2007

Spartan 7 - any new features?

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So after the long mysterious wait since the original announcement, there is finally some information on Spartan-7.  From what I can glean from the latest literature, it seems to be a smaller Artix-7 with no GTP (or PCIe EP).  Am I missing anything?  Are there some new features in Spartan-7 that weren't in Artix-7?  In the advanced data sheet, I see table 26 showing "IO_FIFO" timing characteristics, but no information on what an IO_FIFO is.  Is this a new feature?

-- Gabor
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Guide
Guide
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Registered: ‎01-23-2009

As far as I can tell, Spartan-7 is an Artix-7 without the GTPs. A fair amount of information has been released with the video in this technical blog - all the features described there are the same as the Artix-7. Also, the datasheet (ds189) shows the timing numbers of the fabric to be identical to the Artix-7.

 

The IN_FIFO exists in all the 7 series devices. It is a dedicated shallow FIFO in the IOB. It's primary purpose is for memory controllers, where it can be used to do clock crossing between the DQS (or echo clock for QDR) clock domain and the main memory controller clock domain. It is documented in UG471.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008
We officially release all the details with Vivado 2016.3 which will be in couple of days ! Pleas wait for release . thanks for your curiosity!
Thanks and Regards
Balkrishan
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Guide
Guide
9,717 Views
Registered: ‎01-23-2009

As far as I can tell, Spartan-7 is an Artix-7 without the GTPs. A fair amount of information has been released with the video in this technical blog - all the features described there are the same as the Artix-7. Also, the datasheet (ds189) shows the timing numbers of the fabric to be identical to the Artix-7.

 

The IN_FIFO exists in all the 7 series devices. It is a dedicated shallow FIFO in the IOB. It's primary purpose is for memory controllers, where it can be used to do clock crossing between the DQS (or echo clock for QDR) clock domain and the main memory controller clock domain. It is documented in UG471.

 

Avrum

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008
you can find latest information here
http://www.xilinx.com/products/silicon-devices/fpga/spartan-7.html
Thanks and Regards
Balkrishan
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Adventurer
Adventurer
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Registered: ‎10-14-2013

Is there pin/package compatibility between Aritx-7 / Spartan-7 ?

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