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Visitor rick_mn
Visitor
1,414 Views
Registered: ‎07-20-2010

Spartan II XC2S200-5PQG208I DLL

We are using a DLL in the Spartan 2 with the following instantiation.

The input clock is 40 Mhz, therefore the  clk0 signal is 40 Mhz and the clkdv signal is 16 Mhz.

We have discovered a situation when power cycling and reloading the device after each power on that the clkdv signal

fails to run after a few hundred times.

 

Has anyone seen this condition or know of this?

 

CLKDLL_inst : CLKDLL
 generic map
 (
 CLKDV_DIVIDE => 2.5,    --  Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0
 DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
 FACTORY_JF => X"C080",   --  FACTORY JF Values
 STARTUP_WAIT => TRUE)   --  Delay config DONE until DLL LOCK, TRUE/FALSE
 port map
 (
 CLK0 => clk0,    -- 0 degree DLL CLK ouptput
 CLK180 => open,    -- 180 degree DLL CLK output
 CLK270 => open,    -- 270 degree DLL CLK output
 CLK2X => open,    -- 2X DLL CLK output
 CLK90 => open,    -- 90 degree DLL CLK output
 CLKDV => clkdv,    -- Divided DLL CLK out (CLKDV_DIVIDE)
 LOCKED => dcm_locked,   -- DLL LOCK status output
 CLKFB => clk,     -- DLL clock feedback
 CLKIN => clkin,    -- Clock input (from IBUFG, BUFG or DLL)
 RST  => pwr_on_rst   -- DLL asynchronous reset input
 );

 

Thanks,

Rick

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