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Participant fhknapp44
Participant
3,342 Views
Registered: ‎02-25-2015

Spartan3AN pin assignment problems

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I am using a 700 size -3AN in the FGG484 package and using pads A6 thru A19 (skipping the clocks) and ISE14.7.  The XST function works properly as does the Translate function but the MAP function drops all the pins except for one, A15. These inputs go into conspiratorial logic that is simple. The MAP function just returns messages saying it has 'removed' all these lines in sequence. All of these are designated as general purpose I/O pins except A15. It has an alternate function of being a reference voltage input for Bank0 Differential Inputs.

This is the first time I have used the Spartan series. I have used the Cool-runner series before.

fhknapp44

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Participant fhknapp44
Participant
6,154 Views
Registered: ‎02-25-2015

Re: Spartan3AN pin assignment problems

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U223374: These are the address and control lines from an external source (T.I. XA bus to be exact) with decode logic tied in. So all inputs factor into producing an output of some sort. Maybe the address decode logic is not considered a 'load' by the MAP function?

FHKnapp

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Scholar u4223374
Scholar
3,316 Views
Registered: ‎04-26-2015

Re: Spartan3AN pin assignment problems

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This is virtually always because the combinational logic controlled by these input pins does not drive any output. If there's no output then obviously it doesn't matter whether the inputs are used or not, so Vivado just disconnects them.

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Participant fhknapp44
Participant
6,155 Views
Registered: ‎02-25-2015

Re: Spartan3AN pin assignment problems

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U223374: These are the address and control lines from an external source (T.I. XA bus to be exact) with decode logic tied in. So all inputs factor into producing an output of some sort. Maybe the address decode logic is not considered a 'load' by the MAP function?

FHKnapp

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Xilinx Employee
Xilinx Employee
3,276 Views
Registered: ‎09-05-2007

Re: Spartan3AN pin assignment problems

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I don't think you need to worry about your pin assignments; as U223374 suggested, this almost certainly has something to do with parts of your design being removed (optimised) because they are not required. For example, as you suggest yourself, if your decode isn't actually required in the function that it supposedly drives then it will be removed and the effect will ripple back through to the input pins.

 

As a sanity check, make a quick test design that only contains your address decoder (i.e. an AND gate) with the single output driving an output pin. This shouldn't be removed (unless you have slipped up with signal names somewhere) and would prove your pin assignments are valid (or not).  

Ken Chapman
Principal Engineer, Xilinx UK