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masa6614
Observer
Observer
8,345 Views
Registered: ‎02-12-2010

Spartan3e JTAG problems

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Hi,

I'm trying to program a spartan3e xc3s1600e.  I'm using ISE Impact 11.1 and the Platform Cable USB II.  In Impact,the device shows up when i select 'Initialize Chain'.  I add the configuration bit file to it.  And when i select program I get 'Program Failed' and this shows up.

 

INFO:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File.
INFO:iMPACT:1578 - '1': Device IDCODE : 00001111111111111111111111111110
INFO:iMPACT:1579 - '1': Expected IDCODE: 00000001110000111010000010010011
PROGRESS_END - End Operation.

 I've changed the TCK Speed/Baud Rate to lowest setting, 750 KHz, same error. When I select the chain integrity test, i get a 'CheckIntegrity Failed' and this.

 

 

// *** BATCH CMD : CheckIntegrity
Maximum TCK operating frequency for this device chain: 10000000.
Validating chain...
INFO:iMPACT:1206 - Instruction Capture = '111111010001'
INFO:iMPACT:1207 - Expected Capture = '101010XXXX01'
INFO:iMPACT:2130 - Boundary-scan chain test failed . Please check tdi->tdo connection between the cable and device:'1' ( 'xc3s1600e').
A problem may exist in the hardware configuration.
Check that the cable, scan chain, and power connections are intact,
that the specified scan chain configuration matches the actual hardware, and
that the power supply is adequate and delivering the correct voltage.

I've triple checked my connections on the board, they all seem fine, I'm able to program the fpga from an MCU fine, just not using the jtag.  I've even changed the mode pins m[2:0] from slave parallel to the jtag setting and same problems.

 

 

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mcgett
Xilinx Employee
Xilinx Employee
10,411 Views
Registered: ‎01-03-2008

The likely cause is a failure between the cable TDI pin and the FPGA TDI pin. 

 

When impact scans the JTAG chain, it issues JTAG commands to put all of the TAP controllers into reset, which loads the device IDCODE into the data out register so that it can be clocked out easily for device detection.  This is why impact recognizes the devices when the chain is scanned, but then can't configure the device.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

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4 Replies
austin
Scholar
Scholar
8,337 Views
Registered: ‎02-27-2008

m,

 

Did you check that the power supply was adequate, and the proper voltages are present on the JTAG pins and the JTAG cable (Vref)?

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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masa6614
Observer
Observer
8,335 Views
Registered: ‎02-12-2010

Yeah, monitored all of them, none of them dipped.  Vcco & Vref 3.3V, Vaux 2.5V, and Vint 1.2V.   I've monitored the TCK, TMS, TDI, and TDO while performing a 'Get Device ID' command in Impact, it continues to fail, with the same Device IDCODE read, '00001111111111111111111111111110'. Here's what I'm seeing, and sorry, only one probe on hand at the moment.  TCK was 750kHz and all the signals seems to look clear and not distorted. Any clues? Thanks.

 

TCK

 

 

 

TMS ---------------------------------------------------------------------------------------------------------------------------------

 

 

TDI --------------------------------------------------------------------------------------------------------------------------------

 

 

 

TDO --------------------------------------------------------------------------------------------------------------------------

 

 

Message Edited by masa6614 on 04-07-2010 04:05 PM
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mcgett
Xilinx Employee
Xilinx Employee
10,412 Views
Registered: ‎01-03-2008

The likely cause is a failure between the cable TDI pin and the FPGA TDI pin. 

 

When impact scans the JTAG chain, it issues JTAG commands to put all of the TAP controllers into reset, which loads the device IDCODE into the data out register so that it can be clocked out easily for device detection.  This is why impact recognizes the devices when the chain is scanned, but then can't configure the device.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

View solution in original post

austin
Scholar
Scholar
8,307 Views
Registered: ‎02-27-2008

TDO doesn't look right...

 

It isn't lasting as long as TDI, which implies as Ed suggest, there is a bad connection here somewhere.

 

Could be a solder bridge, or an unsoldered connection.

 

I would start looking at TDI from the cable, to the device as Ed suggests...next I would look at the TCLK at the device, as a bit transitioning when there is no clock edge means that there was an edge there that either you did not see, or the signal you are looking at is not the signal that is actually making it to the die (bad solder joint again).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose