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Explorer
Explorer
706 Views
Registered: ‎03-08-2018

Spartan6 Mapping fail

Jump to solution

Hi,

 

I'v got a Error message during mapping .

Current target board is Spartan6lx16 2C, External input clock is 50Mhz and code is the below.

 

////////////////////////////////////////////////////////////////////////
module HDMI_test(
	input wire pixclk,  // 50MHz
	output wire [2:0] TMDSp, 
	output wire [2:0] TMDSn,
	output wire TMDSp_clock,
	output wire TMDSn_clock
);

////////////////////////////////////////////////////////////////////////
reg [9:0] CounterX, CounterY;
reg hSync, vSync, DrawArea;
always @(posedge pixclk) DrawArea <= (CounterX<640) && (CounterY<480);

always @(posedge pixclk) CounterX <= (CounterX==799) ? 0 : CounterX+1;
always @(posedge pixclk) if(CounterX==799) CounterY <= (CounterY==524) ? 0 : CounterY+1;

always @(posedge pixclk) hSync <= (CounterX>=656) && (CounterX<752);
always @(posedge pixclk) vSync <= (CounterY>=490) && (CounterY<492);

////////////////
wire [7:0] W = {8{CounterX[7:0]==CounterY[7:0]}};
wire [7:0] A = {8{CounterX[7:5]==3'h2 && CounterY[7:5]==3'h2}};
reg [7:0] red, green, blue;
always @(posedge pixclk) red <= ({CounterX[5:0] & {6{CounterY[4:3]==~CounterX[4:3]}}, 2'b00} | W) & ~A;
always @(posedge pixclk) green <= (CounterX[7:0] & {8{CounterY[6]}} | W) & ~A;
always @(posedge pixclk) blue <= CounterY[7:0] | W | A;

////////////////////////////////////////////////////////////////////////
wire [9:0] TMDS_red, TMDS_green, TMDS_blue;
TMDS_encoder encode_R(.clk(pixclk), .VD(red  ), .CD(2'b00)        , .VDE(DrawArea), .TMDS(TMDS_red));
TMDS_encoder encode_G(.clk(pixclk), .VD(green), .CD(2'b00)        , .VDE(DrawArea), .TMDS(TMDS_green));
TMDS_encoder encode_B(.clk(pixclk), .VD(blue ), .CD({vSync,hSync}), .VDE(DrawArea), .TMDS(TMDS_blue));

////////////////////////////////////////////////////////////////////////
wire clk_TMDS, DCM_TMDS_CLKFX;  // 50MHz x 5 = 250MHz
DCM_SP #(.CLKFX_MULTIPLY(5)) DCM_TMDS_inst(.CLKIN(pixclk), .CLKFX(DCM_TMDS_CLKFX), .RST(1'b0));
BUFG BUFG_TMDSp(.I(DCM_TMDS_CLKFX), .O(clk_TMDS));

////////////////////////////////////////////////////////////////////////
reg [3:0] TMDS_mod10=0;  // modulus 10 counter
reg [9:0] TMDS_shift_red=0, TMDS_shift_green=0, TMDS_shift_blue=0;
reg TMDS_shift_load=0;
always @(posedge clk_TMDS) TMDS_shift_load <= (TMDS_mod10==4'd9);

always @(posedge clk_TMDS)
begin
	TMDS_shift_red   <= TMDS_shift_load ? TMDS_red   : TMDS_shift_red  [9:1];
	TMDS_shift_green <= TMDS_shift_load ? TMDS_green : TMDS_shift_green[9:1];
	TMDS_shift_blue  <= TMDS_shift_load ? TMDS_blue  : TMDS_shift_blue [9:1];	
	TMDS_mod10 <= (TMDS_mod10==4'd9) ? 4'd0 : TMDS_mod10+4'd1;
end

OBUFDS OBUFDS_red  (.I(TMDS_shift_red  [0]), .O(TMDSp[2]), .OB(TMDSn[2]));
OBUFDS OBUFDS_green(.I(TMDS_shift_green[0]), .O(TMDSp[1]), .OB(TMDSn[1]));
OBUFDS OBUFDS_blue (.I(TMDS_shift_blue [0]), .O(TMDSp[0]), .OB(TMDSn[0]));
OBUFDS OBUFDS_clock(.I(pixclk), .O(TMDSp_clock), .OB(TMDSn_clock));
endmodule


////////////////////////////////////////////////////////////////////////
module TMDS_encoder(
	input clk,
	input [7:0] VD,  // video data (red, green or blue)
	input [1:0] CD,  // control data
	input VDE,  // video data enable, to choose between CD (when VDE=0) and VD (when VDE=1)
	output reg [9:0] TMDS = 0
);

wire [3:0] Nb1s = VD[0] + VD[1] + VD[2] + VD[3] + VD[4] + VD[5] + VD[6] + VD[7];
wire XNOR = (Nb1s>4'd4) || (Nb1s==4'd4 && VD[0]==1'b0);
wire [8:0] q_m = {~XNOR, q_m[6:0] ^ VD[7:1] ^ {7{XNOR}}, VD[0]};

reg [3:0] balance_acc = 0;
wire [3:0] balance = q_m[0] + q_m[1] + q_m[2] + q_m[3] + q_m[4] + q_m[5] + q_m[6] + q_m[7] - 4'd4;
wire balance_sign_eq = (balance[3] == balance_acc[3]);
wire invert_q_m = (balance==0 || balance_acc==0) ? ~q_m[8] : balance_sign_eq;
wire [3:0] balance_acc_inc = balance - ({q_m[8] ^ ~balance_sign_eq} & ~(balance==0 || balance_acc==0));
wire [3:0] balance_acc_new = invert_q_m ? balance_acc-balance_acc_inc : balance_acc+balance_acc_inc;
wire [9:0] TMDS_data = {invert_q_m, q_m[8], q_m[7:0] ^ {8{invert_q_m}}};
wire [9:0] TMDS_code = CD[1] ? (CD[0] ? 10'b1010101011 : 10'b0101010100) : (CD[0] ? 10'b0010101011 : 10'b1101010100);

always @(posedge clk) TMDS <= VDE ? TMDS_data : TMDS_code;
always @(posedge clk) balance_acc <= VDE ? balance_acc_new : 4'h0;
endmodule


////////////////////////////////////////////////////////////////////////

The Error message is the below

 

 

Running directed packing...
ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOBS component because the site type selected is not compatible. 

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOBS was chosen because the IO contains symbols and/or properties consistent
   with differential slave usage. Please double check that the types of logic
   elements and all of their relevant properties and configuration options are
   compatible with the physical site type of the constraint.

   Summary:
   Symbols involved:
   	PAD symbol "TMDSn_clock" (Pad Signal = TMDSn_clock)
   	SlaveBuffer symbol "OBUFDS_clock/SLAVEBUF.DIFFOUT" (Output Signal =
   TMDSn_clock)
   Component type involved: IOBS
   Site Location involved: B14
   Site Type involved: IOBM


Mapping completed.
See MAP report file "HDMI_test_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors   :   1
Number of warnings :   0

Process "Map" failed

 

I can't understand this error.

What am I supposed to do to resolve this problem?

 

 

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
879 Views
Registered: ‎11-30-2007

Re: Spartan6 Mapping fail

Jump to solution

You didn't provide your UCF file for pin location constraints.  Which XC6SLX16-2xxxxxC package?

 

CPG196 (dedicated pin - TMS)
CSG225 (IO_L1P_A25_1; B15 is IO_L1N_A24_VERF_1)
CSG324 (IO_L62P_0; A14 IO_L62N_VREF_0)
FTG256 (IO_L65P_SCP3_0; A14 IO_65N_SCP2_0)

 

At quick glance, it appears you assigned the "N" side of the differential pair to the "P" side of the pin-pair.

 

I would expect the following pin mapping:

 

CSG225

TMDSp_clock = B14 (P side)

TMDSn_clock = B15 (N side)

 

CSG324

TMDSp_clock = B14 (P side)

TMDSn_clock = A14 (N side)

 

FTG256

TMDSp_clock = B14 (P side)

TMDSn_clock = A14 (N side)

 

I hope this helps.

 

3 Replies
Xilinx Employee
Xilinx Employee
880 Views
Registered: ‎11-30-2007

Re: Spartan6 Mapping fail

Jump to solution

You didn't provide your UCF file for pin location constraints.  Which XC6SLX16-2xxxxxC package?

 

CPG196 (dedicated pin - TMS)
CSG225 (IO_L1P_A25_1; B15 is IO_L1N_A24_VERF_1)
CSG324 (IO_L62P_0; A14 IO_L62N_VREF_0)
FTG256 (IO_L65P_SCP3_0; A14 IO_65N_SCP2_0)

 

At quick glance, it appears you assigned the "N" side of the differential pair to the "P" side of the pin-pair.

 

I would expect the following pin mapping:

 

CSG225

TMDSp_clock = B14 (P side)

TMDSn_clock = B15 (N side)

 

CSG324

TMDSp_clock = B14 (P side)

TMDSn_clock = A14 (N side)

 

FTG256

TMDSp_clock = B14 (P side)

TMDSn_clock = A14 (N side)

 

I hope this helps.

 

Explorer
Explorer
670 Views
Registered: ‎03-08-2018

Re: Spartan6 Mapping fail

Jump to solution

@miker

 

my target board is FTG256.

 

Sorry, my ucf modified as the below,

 

//global system clock
NET "pixclk" 		LOC = A10 	| IOSTANDARD = LVTTL;

//# HDMI Out (J3)
NET "TMDSp_clock" LOC = "A13" | IOSTANDARD = TMDS_33 ; # Clock
NET "TMDSn_clock" LOC = "A14" | IOSTANDARD = TMDS_33 ;
NET "TMDSp[0]"  	LOC = "A9"  | IOSTANDARD = TMDS_33 ; # Blue
NET "TMDSn[0]"  	LOC = "C11" | IOSTANDARD = TMDS_33 ;
NET "TMDSp[1]"  	LOC = "A11" | IOSTANDARD = TMDS_33 ; # Red
NET "TMDSn[1]"  	LOC = "B12" | IOSTANDARD = TMDS_33 ;
NET "TMDSp[2]"  	LOC = "A12" | IOSTANDARD = TMDS_33 ; # Green
NET "TMDSn[2]"  	LOC = "C13" | IOSTANDARD = TMDS_33 ;



and I've got bunch of error messages as the below,

 

 

Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "D:/work/HDMI/HDMI_test/spartan6_hdmi/HDMI_test.xst" -ofn "D:/work/HDMI/HDMI_test/spartan6_hdmi/HDMI_test.syr"
Reading design: HDMI_test.prj

=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "D:\work\HDMI\HDMI_test\spartan6_hdmi\HDMI_test.v" into library work
Parsing module <HDMI_test>.
Parsing module <TMDS_encoder>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================
WARNING:HDLCompiler:1016 - "D:\work\HDMI\HDMI_test\spartan6_hdmi\HDMI_test.v" Line 39: Port CLK0 is not connected to this instance

Elaborating module <HDMI_test>.
WARNING:HDLCompiler:413 - "D:\work\HDMI\HDMI_test\spartan6_hdmi\HDMI_test.v" Line 17: Result of 32-bit expression is truncated to fit in 10-bit target.
WARNING:HDLCompiler:413 - "D:\work\HDMI\HDMI_test\spartan6_hdmi\HDMI_test.v" Line 18: Result of 32-bit expression is truncated to fit in 10-bit target.

Elaborating module <TMDS_encoder>.

Elaborating module <DCM_SP(CLKFX_MULTIPLY=5)>.

Elaborating module <BUFG>.

Elaborating module <OBUFDS>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <HDMI_test>.
    Related source file is "D:\work\HDMI\HDMI_test\spartan6_hdmi\HDMI_test.v".
    Found 10-bit register for signal <CounterX>.
    Found 10-bit register for signal <CounterY>.
    Found 1-bit register for signal <hSync>.
    Found 1-bit register for signal <vSync>.
    Found 8-bit register for signal <red>.
    Found 8-bit register for signal <green>.
    Found 8-bit register for signal <blue>.
    Found 1-bit register for signal <TMDS_shift_load>.
    Found 10-bit register for signal <TMDS_shift_red>.
    Found 10-bit register for signal <TMDS_shift_green>.
    Found 10-bit register for signal <TMDS_shift_blue>.
    Found 4-bit register for signal <TMDS_mod10>.
    Found 1-bit register for signal <DrawArea>.
    Found 11-bit adder for signal <n0103[10:0]> created at line 17.
    Found 11-bit adder for signal <n0105[10:0]> created at line 18.
    Found 4-bit adder for signal <TMDS_mod10[3]_GND_1_o_add_49_OUT> created at line 53.
    Found 10-bit comparator greater for signal <CounterX[9]_PWR_1_o_LessThan_2_o> created at line 15
    Found 10-bit comparator greater for signal <CounterY[9]_GND_1_o_LessThan_3_o> created at line 15
    Found 10-bit comparator lessequal for signal <n0013> created at line 20
    Found 10-bit comparator greater for signal <CounterX[9]_PWR_1_o_LessThan_18_o> created at line 20
    Found 10-bit comparator lessequal for signal <n0018> created at line 21
    Found 10-bit comparator greater for signal <CounterY[9]_GND_1_o_LessThan_21_o> created at line 21
    Found 8-bit comparator equal for signal <W<7>> created at line 24
    Found 2-bit comparator equal for signal <CounterY[4]_CounterX[4]_equal_27_o> created at line 27
    Summary:
	inferred   3 Adder/Subtractor(s).
	inferred  82 D-type flip-flop(s).
	inferred   8 Comparator(s).
	inferred   4 Multiplexer(s).
Unit <HDMI_test> synthesized.

Synthesizing Unit <TMDS_encoder>.
    Related source file is "D:\work\HDMI\HDMI_test\spartan6_hdmi\HDMI_test.v".
    Found 4-bit register for signal <balance_acc>.
    Found 10-bit register for signal <TMDS>.
    Found 4-bit subtractor for signal <balance_acc_inc> created at line 80.
    Found 4-bit subtractor for signal <balance_acc[3]_balance_acc_inc[3]_sub_29_OUT> created at line 81.
    Found 2-bit adder for signal <n0109[1:0]> created at line 72.
    Found 3-bit adder for signal <n0112[2:0]> created at line 72.
    Found 2-bit adder for signal <n0130[1:0]> created at line 77.
    Found 3-bit adder for signal <n0133[2:0]> created at line 77.
    Found 4-bit adder for signal <balance_acc[3]_balance_acc_inc[3]_add_29_OUT> created at line 81.
    Found 4-bit adder for signal <_n0160> created at line 72.
    Found 4-bit adder for signal <_n0161> created at line 72.
    Found 4-bit adder for signal <_n0162> created at line 72.
    Found 4-bit adder for signal <_n0163> created at line 72.
    Found 4-bit adder for signal <Nb1s> created at line 72.
    Found 4-bit adder for signal <_n0165> created at line 77.
    Found 4-bit subtractor for signal <_n0166> created at line 77.
    Found 4-bit adder for signal <_n0167> created at line 77.
    Found 4-bit adder for signal <_n0168> created at line 77.
    Found 4-bit adder for signal <_n0169> created at line 77.
    Found 4-bit adder for signal <balance> created at line 77.
    Found 4-bit comparator greater for signal <GND_2_o_Nb1s[3]_LessThan_8_o> created at line 73
    Found 1-bit comparator equal for signal <balance_sign_eq> created at line 78
    Summary:
	inferred  17 Adder/Subtractor(s).
	inferred  14 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred   3 Multiplexer(s).
Unit <TMDS_encoder> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 54
 11-bit adder                                          : 2
 2-bit adder                                           : 6
 3-bit adder                                           : 6
 4-bit adder                                           : 31
 4-bit addsub                                          : 3
 4-bit subtractor                                      : 6
# Registers                                            : 18
 1-bit register                                        : 2
 10-bit register                                       : 8
 2-bit register                                        : 1
 4-bit register                                        : 4
 8-bit register                                        : 3
# Comparators                                          : 14
 1-bit comparator equal                                : 3
 10-bit comparator greater                             : 4
 10-bit comparator lessequal                           : 2
 2-bit comparator equal                                : 1
 4-bit comparator greater                              : 3
 8-bit comparator equal                                : 1
# Multiplexers                                         : 13
 1-bit 2-to-1 multiplexer                              : 3
 10-bit 2-to-1 multiplexer                             : 9
 32-bit 2-to-1 multiplexer                             : 1
# Xors                                                 : 12
 1-bit xor2                                            : 3
 7-bit xor2                                            : 6
 8-bit xor2                                            : 3

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <HDMI_test>.
The following registers are absorbed into counter <TMDS_mod10>: 1 register on signal <TMDS_mod10>.
The following registers are absorbed into counter <CounterX>: 1 register on signal <CounterX>.
Unit <HDMI_test> synthesized (advanced).

Synthesizing (advanced) Unit <TMDS_encoder>.
The following registers are absorbed into accumulator <balance_acc>: 1 register on signal <balance_acc>.
	The following adders/subtractors are grouped into adder tree <Madd_balance_Madd1> :
 	<Madd__n0169_Madd> in block <TMDS_encoder>, 	<Madd_n0130[1:0]> in block <TMDS_encoder>, 	<Madd_balance_Madd> in block <TMDS_encoder>.
	The following adders/subtractors are grouped into adder tree <Madd_Nb1s_Madd1> :
 	<Madd__n0160> in block <TMDS_encoder>, 	<Madd__n0161> in block <TMDS_encoder>, 	<Madd__n0163_Madd> in block <TMDS_encoder>, 	<Madd_n0109[1:0]> in block <TMDS_encoder>, 	<Madd_Nb1s_Madd> in block <TMDS_encoder>.
Unit <TMDS_encoder> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 10
 11-bit adder                                          : 1
 4-bit adder carry in                                  : 3
 4-bit subtractor                                      : 6
# Adder Trees                                          : 6
 4-bit / 4-inputs adder tree                           : 3
 4-bit / 6-inputs adder tree                           : 3
# Counters                                             : 2
 10-bit up counter                                     : 1
 4-bit up counter                                      : 1
# Accumulators                                         : 3
 4-bit updown accumulator                              : 3
# Registers                                            : 98
 Flip-Flops                                            : 98
# Comparators                                          : 14
 1-bit comparator equal                                : 3
 10-bit comparator greater                             : 4
 10-bit comparator lessequal                           : 2
 2-bit comparator equal                                : 1
 4-bit comparator greater                              : 3
 8-bit comparator equal                                : 1
# Multiplexers                                         : 13
 1-bit 2-to-1 multiplexer                              : 3
 10-bit 2-to-1 multiplexer                             : 9
 32-bit 2-to-1 multiplexer                             : 1
# Xors                                                 : 12
 1-bit xor2                                            : 3
 7-bit xor2                                            : 6
 8-bit xor2                                            : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:2261 - The FF/Latch <red_0> in Unit <HDMI_test> is equivalent to the following FF/Latch, which will be removed : <red_1> 

Optimizing unit <HDMI_test> ...

Optimizing unit <TMDS_encoder> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block HDMI_test, actual ratio is 3.
Preparing to edit spartan6_hdmi.ucf...

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 123
 Flip-Flops                                            : 123

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
pixclk                             | IBUFG+BUFG             | 88    |
pixclk                             | DCM_SP:CLKFX           | 35    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -2

   Minimum period: 12.600ns (Maximum Frequency: 79.365MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 4.118ns
   Maximum combinational path delay: 4.921ns

=========================================================================

Process "Synthesize - XST" completed successfully

Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc spartan6_hdmi.ucf -p xc6slx16-ftg256-2 HDMI_test.ngc HDMI_test.ngd

Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -nt timestamp -uc spartan6_hdmi.ucf -p xc6slx16-ftg256-2
HDMI_test.ngc HDMI_test.ngd

Reading NGO file "D:/work/HDMI/HDMI_test/spartan6_hdmi/HDMI_test.ngc" ...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "spartan6_hdmi.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "HDMI_test.ngd" ...
Total REAL time to NGDBUILD completion:  2 sec
Total CPU time to NGDBUILD completion:   2 sec

Writing NGDBUILD log file "HDMI_test.bld"...

NGDBUILD done.

Process "Translate" completed successfully

Started : "Map".
Running map...
Command Line: map -intstyle ise -p xc6slx16-ftg256-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o HDMI_test_map.ncd HDMI_test.ngd HDMI_test.pcf
Using target part "6slx16ftg256-2".
Mapping design into LUTs...
Running directed packing...
ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOBM component because the site type selected is not compatible. 

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOBM was chosen because the IO contains an true differential buffer symbol.
   Please double check that the types of logic elements and all of their
   relevant properties and configuration options are compatible with the
   physical site type of the constraint.

   Summary:
   Symbols involved:
   	PAD symbol "TMDSp_clock" (Pad Signal = TMDSp_clock)
   	BUFINV symbol "OBUFDS_clock/OBUFDS" (Output Signal = TMDSp_clock)
   Component type involved: IOBM
   Site Location involved: A13
   Site Type involved: IOBS

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOBS component because the site type selected is not compatible. 

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOBS was chosen because the IO contains symbols and/or properties consistent
   with differential slave usage. Please double check that the types of logic
   elements and all of their relevant properties and configuration options are
   compatible with the physical site type of the constraint.

   Summary:
   Symbols involved:
   	PAD symbol "TMDSn<0>" (Pad Signal = TMDSn<0>)
   	SlaveBuffer symbol "OBUFDS_blue/SLAVEBUF.DIFFOUT" (Output Signal = TMDSn<0>)
   Component type involved: IOBS
   Site Location involved: C11
   Site Type involved: IOBM

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOBS component because the site type selected is not compatible. 

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOBS was chosen because the IO contains symbols and/or properties consistent
   with differential slave usage. Please double check that the types of logic
   elements and all of their relevant properties and configuration options are
   compatible with the physical site type of the constraint.

   Summary:
   Symbols involved:
   	PAD symbol "TMDSn<1>" (Pad Signal = TMDSn<1>)
   	SlaveBuffer symbol "OBUFDS_green/SLAVEBUF.DIFFOUT" (Output Signal =
   TMDSn<1>)
   Component type involved: IOBS
   Site Location involved: B12
   Site Type involved: IOBM

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOBS component because the site type selected is not compatible. 

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOBS was chosen because the IO contains symbols and/or properties consistent
   with differential slave usage. Please double check that the types of logic
   elements and all of their relevant properties and configuration options are
   compatible with the physical site type of the constraint.

   Summary:
   Symbols involved:
   	PAD symbol "TMDSn<2>" (Pad Signal = TMDSn<2>)
   	SlaveBuffer symbol "OBUFDS_red/SLAVEBUF.DIFFOUT" (Output Signal = TMDSn<2>)
   Component type involved: IOBS
   Site Location involved: C13
   Site Type involved: IOBM

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOBM component because the site type selected is not compatible. 

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOBM was chosen because the IO contains an true differential buffer symbol.
   Please double check that the types of logic elements and all of their
   relevant properties and configuration options are compatible with the
   physical site type of the constraint.

   Summary:
   Symbols involved:
   	PAD symbol "TMDSp<0>" (Pad Signal = TMDSp<0>)
   	BUFINV symbol "OBUFDS_blue/OBUFDS" (Output Signal = TMDSp<0>)
   Component type involved: IOBM
   Site Location involved: A9
   Site Type involved: IOBS

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOBM component because the site type selected is not compatible. 

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOBM was chosen because the IO contains an true differential buffer symbol.
   Please double check that the types of logic elements and all of their
   relevant properties and configuration options are compatible with the
   physical site type of the constraint.

   Summary:
   Symbols involved:
   	PAD symbol "TMDSp<1>" (Pad Signal = TMDSp<1>)
   	BUFINV symbol "OBUFDS_green/OBUFDS" (Output Signal = TMDSp<1>)
   Component type involved: IOBM
   Site Location involved: A11
   Site Type involved: IOBS

ERROR:Pack:1107 - Pack was unable to combine the symbols listed below into a
   single IOBM component because the site type selected is not compatible. 

   Further explanation:
   The component type is determined by the types of logic and the properties and
   configuration of the logic it contains. In this case an IO component of type
   IOBM was chosen because the IO contains an true differential buffer symbol.
   Please double check that the types of logic elements and all of their
   relevant properties and configuration options are compatible with the
   physical site type of the constraint.

   Summary:
   Symbols involved:
   	PAD symbol "TMDSp<2>" (Pad Signal = TMDSp<2>)
   	BUFINV symbol "OBUFDS_red/OBUFDS" (Output Signal = TMDSp<2>)
   Component type involved: IOBM
   Site Location involved: A12
   Site Type involved: IOBS


Mapping completed.
See MAP report file "HDMI_test_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors   :   7
Number of warnings :   0

Process "Map" failed
Preparing to edit spartan6_hdmi.ucf...

 

 

Would you let me know where did you find that information?

 

Currently I've got SCH as the below.

q97.jpg

 

 

Would you please recommend what am I supposed to connect between them?

 

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Xilinx Employee
Xilinx Employee
661 Views
Registered: ‎11-30-2007

Re: Spartan6 Mapping fail

Jump to solution

As an example, you could use the following pinout:

 

#global system clock
NET "pixclk"   LOC = "A10"  | IOSTANDARD = LVTTL;

## HDMI Out (J3)
NET "TMDSp_clock" LOC = "B14" | IOSTANDARD = TMDS_33 ; # Clock
NET "TMDSn_clock" LOC = "A14" | IOSTANDARD = TMDS_33 ;
NET "TMDSp[0]"   LOC = "C9"  | IOSTANDARD = TMDS_33 ; # Blue
NET "TMDSn[0]"   LOC = "A9"  | IOSTANDARD = TMDS_33 ;
NET "TMDSp[1]"   LOC = "C11" | IOSTANDARD = TMDS_33 ; # Red
NET "TMDSn[1]"   LOC = "A11" | IOSTANDARD = TMDS_33 ;
NET "TMDSp[2]"   LOC = "B12" | IOSTANDARD = TMDS_33 ; # Green
NET "TMDSn[2]"   LOC = "A12" | IOSTANDARD = TMDS_33 ;

 

You can reference the Spartan-6 FPGA SelectIO Resources User Guide (UG381; v1.7) under the section Differential I/O Standards on p36.

 

S6_diff_io.png