Spartan6 pcb guidelines ug393 decoupling capacitor

[deng8803]

    I am designing a schemetic and PCB with a Spartan6LX9_FTG256 and intend to follow the decoupling capacitor recommendations  but I am looking for some addition information in regards to the placement and routing of the recommended caps.

    Using my chip as an example, UG939 recommends the  LX9_FTG256 have 1x100uf / 3x4.7uf / 1x0.47uf caps for Vccint ( 5 total caps). My interest is how to most effectively connet these capacitors over the 8 Vccint pins.

i am looking forward for a reply, thx. 

and any material in regards to this issue would be appreciated.

[austin]

d,

Check out the schematics and layout of one of the demo boards Xilinx sells. We tend to use our own guidelines.

[eteam00]

Smallest (and lowest value) caps should be nearest the power supply pins of the powered (load) device.  These are in addition to the local decoupling caps recommended by the regulator manufacturer.

Largest (bulk) caps can be anywhere, as long as the path impedance between the cap and power supply island or plane is reasonably low (4 nearby vias to power plane and 4 nearby vias to GND plane should be fine).

It is always best to place decoupling caps between power source (e.g. regulator) and load, to minimise power supply and GND plane currents.  This helps reduce board radiated emissions, ground voltage offsets, board's electrical 'noise', etc.

On the subject of capacitor selection, the following excerpt from one of my past posts summarises everything else I know on the subject, and more.

I've been designing digital logic boards for 30 years, including FPGAs.  Here is what I use on my latest board:

For 1-per-pin power supply decoupling:  1uF 0402 X5R ceramic chip cap - cheap is fine, buy from a top-tier parts distributor.  In modest volume, these are less than 1 cent apiece.

For "bulk" decoupling:  I pick the largest capacity 0805-sized X5R MLCC cap I can find which is readily available (and alternate sourced), also from a top-tier distributor.  Depending on switching supply frequency, I spread enough of them around to accumulate double the calculated requirement for aggregate bulk capacity.  This year, I'm using 10uF 16V X5R 0805 caps for bulk decoupling (almost) throughout my boards.  In modest volumes, these caps are around 5 cents apiece.

It is better to use 10 10uF caps than to use a single big honkin' 100uF cap.  The effective ESR (or impedance) is much lower when using multiple caps vs. a single cap.  Also, layout guys prefer smaller parts, in general, and I agree with them.  Smaller parts are easier to place where they are useful.

Generally speaking, the highest capacitance in the smallest package is guaranteed by construction to be low-ESR.

For the 1-per-pin decoupling cap, any (X5R) value from 0.1UF to 1UF should be fine.  In the old days of through-hole components, smaller capacitance meant lower inductance and lower ESR.  In the days of MLCC caps, the opposite is true.  The largest capacitance in a given package size is likely to also have the lowest inductance and lowest ESR.  Because 1uF 0402 caps cost about the same as 0.1UF 0402 caps, I use the 1UF caps.  Using 1uF caps also means that I don't think twice about having enough bulk capacitance.

You should learn some basics about capacitors and their construction, terminology, etc., so you avoid silly mistakes (e.g. picking a Y5V cap when you really want an X5R cap).

The selection of capacitors (like connectors) is bewildering.  There are many acceptable choices.  Xilinx makes specific recommendations so that newbies like you won't hyper-ventilate with stress from fear and uncertainty.  I'm well past the point of hyper-ventilation, and I realise that the Xilinx recommendation isn't the ONLY path to reliable design.  Until you get a few designs under your belt, you'll likely sleep better if you follow the Xilinx recommendations.

There are several different approaches you can take to capacitor selection, all of which can be successful:

• Copy from a similar board (e.g. Xilinx development board)
• Copy from similar boards in your company (and share the same parts inventory) -- stick with what works
• Follow manufacturer (e.g. Xilinx, Intel, freescale, Micron, Samsung, etc.) recommendations
• Consult an analogue design or power supply design guru.
• Become immersed in the theory and practice of capacitors, packages, and board layout -- and become your own guru.
• A combination of all of the above.

Good luck to you, and sleep well.

-- Bob Elkind

[gszakacs]

One more caveat for bypass cap placement.  Many boards use split power planes, especially for

nets like Vccint which aren't likely to be used by other chips on the board.  Make sure all of your

bypass caps, including the large ones, are in the poured plane area that includes the FPGA.

Bypassing on the other end of a routed net is useless.  If your power regulator is located on

the other end of a route (make sure it's wide enough to supply the average current) it may

also need capacitance at the regulator for stability, but don't count this in your FPGA chip

bypass count.  Note that FPGA's have a very large dynamic power component, so even the

largest caps are necessary to deal with the changes in load.  I have had Virtex 2 boards

that lost their configuration due to sudden current draw causing a droop in Vccint.  I fixed the

problem with a couple of 22uF ceramics near the FPGA.  Also - As Bob pointed out you're

better off with more smaller caps than one big one, but if you decide to use a big one, make

sure it has very low ESR and use multiple vias to the plane from each pad to handle the

current and recude inductance.

Remember that the schematics only provide parts that make the design possible -

the layout is a large part of the circuit.  You can copy an eval board schematic exactly

and have a completely unworkable design if it is not properly laid out and routed.

-- Gabor

[eteam00]

Remember that the schematics only provide parts that make the design possible - the layout is a large part of the circuit. You can copy an eval board schematic exactly and have a completely unworkable design if it is not properly laid out and routed.

Dittoes to Gabor's comments.  Wise words!

-- Bob Elkind

[drjohnsmith]

Wise words guys,

   now if someone can wrap that up into a one page note for the sticky area, that would be good.

My little input, and it is only that.

debugging insufficient or wrongly placed decoupling is a real night mare.

     it will hit you randomly , at the worst time of night just before an important dead line.

so be conservartive, you can always de populate later if you need to save a bit.

[eteam00]

now if someone can wrap that up into a one page note for the sticky area, that would be good

The Xilinx-written PCB Design Guidelines (UG393) and similar docs are provided for designers who want or need some guidance.

-- Bob Elkind

[drjohnsmith]

Thanks Bob

I totaly agree with you, there are lots of user guides , as is said earlier in this thread.

I was thinking more of the bits like your comments, 

     they are not  in and I think they do not fit in a user guide doc well,

but this forum has a PLD blog,  that people like Austin put notes in, 

     a wrap up of these and a few more notes might fit well in there,

           and in future we can point people at that blog,

just a thought

[yangjingaus@gmail.com]

Hi, I use to design Spartan 3 using 100nF 1nF decoupling as recommended, I am interesting to know why it is so big difference between Spartan 6 and 3 in terms of the decoupling capacitors, Is there any manufacture technology defference in between?  Thx.

---

[gszakacs]

---

@yangjingaus@gmail.com wrote:

Hi, I use to design Spartan 3 using 100nF 1nF decoupling as recommended, I am interesting to know why it is so big difference between Spartan 6 and 3 in terms of the decoupling capacitors, Is there any manufacture technology defference in between?  Thx.

---

---

There are definitely differences in the manufacturing process between S3 and S6, but also there

have been advances in multilayer ceramic capacitors over the same time period.  The recommendations

for S6 take into account the changes in ceramic capacitors, the largest of which is that you can get

much more capacitance in a small package and still have a high crossover frequency.  The old

rule of using 100 nF was based on that being the largest reasonable value in a small footprint.

-- Gabor

[drjohnsmith]

differance between 3 and 6 ?

    different processes, differnet pin out / construction

        different IO voltages and drivers.

all adds up to, an easier to drive FPGA, 

   but as always, we increase what we want the fpga to do,

       so it all comes around,

just follow the rules, and all should be well,

[yangjingaus@gmail.com]

Gabor,

Thanks for reply. I noticed spartan 6 integrated some decoupling caps in package. I tried to find how much value of those substrate capacitor added to each power pin in the package of spartan 6, but failed. Is Xilinx able to provide this kind of info?

[eteam00]

I noticed spartan 6 integrated some decoupling caps in package. I tried to find how much value of those substrate capacitor added to each power pin in the package of spartan 6, but failed.

I had read this was true for Virtex-6 packages (integrated decoupling caps), but didn't realise this was practiced with Spartan-6 devices as well.

-- Bob Elkind

[yangjingaus@gmail.com]

Virtex 6 share the same architeture with spartan 6, however, there is no such info specify the value of the substrate decoupling caps on each power pins, even for Virtex 6. I can only find something with Virtex 5.  So, I wonder if Xilinx can give a clue?

[eteam00]

Virtex 6 share the same architeture with spartan 6

For packaging?  No.

Spartan-6 uses low-cost packages with wire-bonded pads, Virtex-6 uses flip-chip packages.  (Ref:  page 1 of DS150 and DS160).  Virtex-6 packages incorporate substrate decoupling caps (UG373 v1.2  page 23), Spartan-6 packages do not.

As a consequence, the board decoupling supply caps recommendations for Spartan-6 and Virtex-6 are very different from one another.

-- Bob Elkind

[yangjingaus@gmail.com]

ok, thanks.

[kurgan]

Hello,

I`m former Altera user and long-time Xilinx user.

I agree and disagree too :)

Right solution for capacitor selection - using PDN calculation and/or sumulation.

See this link for example

http://www.altera.com/technology/signal/power-distribution-network/sgl-pdn.html

Selection of caps not only searching cheap parts at Digi.

Good PDN design provide low power plane impedanse at given frequency band.

Unfortunatelly Xilinx not provide any PDN calculators :(

Will use Altera tools for Xilinx design :)

-- Regards, Victor

[eteam00]

Right solution for capacitor selection - using PDN calculation and/or simulation.

Understanding the underlying concepts, theory, and practical details is very useful.  On the other hand, if all the theory and science can be summarised in what some people call "rules of thumb", this makes life simpler for many designers.

For example:

When you drive your auto to the filling station, do you check the compression of your engine, the atmospheric pressure, the ambient humidity and temperature, and the ignition timing of your auto's spark generator before selecting which octane rating of petrol to purchase?  Or do you simply accept the manufacturer's recommendation for octane rating 87, as a reasonable and practical summation of expert analysis and calculation which has been done on your behalf?

The Xilinx board design recommendations for decoupling caps are intended to be a reasonable and practical summation of expert analysis and calculation.  Such summations are possible and practical because the problem of decoupling capacitor selection isn't all that difficult.  The advent of high-quality MLCC surface mount capacitors, replacing leaded ceramic and aluminum capacitors, has greatly simplified the task of providing a competent solution.

See this link for example

The linked white paper is excellent.  The attention given to layout and board stack-up considerations is very helpful.

Selection of caps not only searching cheap parts at Digi.

You have over-simplified, Victor.  Read my comments again.  X5R capacitors are not the cheapest parts -- they are the high-quality fine-tolerance stable parts.  The cheapest X5R caps (from a reputable distributor and manufacturer) are not the cheapest caps.

Good PDN design provide low power plane impedanse at given frequency band.

Unfortunatelly Xilinx not provide any PDN calculators :(

Providing a reliable and cost-effective solution -- for capacitor selection -- is not that difficult, and the guidance provided by Xilinx is in the form of easy-to-follow instructions.  I have my own "rule of thumb" practice which is also reliable and cost-effective.   My approach is not the only correct one, and the success of my approach does not mean that the Xilinx recommendations are flawed -- they are not.

One of the purposes of this thread is to reduce level of fear, uncertainty, doubt, and anxiety of FPGA/board designers where capacitor selection and layout decisions must be made.

It is one thing to say 'here is a white paper on the underlying principles and considerations, in case you are interested'.

It is quite another matter to say (or imply)  'nothing you have read from these folks is safe and reliable, the only proper guidance is from this PDN calculator'.  This would be both untrue and counter-productive.

-- Bob Elkind

[kurgan]

Hello,

Worst case scenario

Basically FPGA is not alone on PCB.

I can have 20 packages from 5 vendors.

Each vendors recommend use different capacitors for chips decoupling.

And component management department kill me if I will use 20 different cap. values.

---

Fable summary.

1) You shoud know PDN design principles

2) You can follow or not follow chip vendors recommendation at own risk in both cases

3) You can use PDN design and propose reading decoupling recommendation to grandmother. :)

-- Best Regards (and good decoupling :) )

Victor

[gszakacs]

Fable summary.

1) You shoud know PDN design principles

agreed!

2) You can follow or not follow chip vendors recommendation at own risk in both cases

True, but risk is near zero if you follow point 1)

3) You can use PDN design and propose reading decoupling recommendation to grandmother. :)

Or use your own noodle to place components that you are familiar with and know work.

Basically FPGA is not alone on PCB.

I can have 20 packages from 5 vendors.

Each vendors recommend use different capacitors for chips decoupling.

No one says you have to use the values proposed by vendors, just like you don't have to

copy the eval board schematics.  They are given as a starting point because they have

been shown to work on the eval board.

And component management department kill me if I will use 20 different cap. values.

Maybe it's time to fire the "component management department" and use their salary

to allow better component selection on your next design.  Either that or hire some

"component managers" who have the skill to do your board decoupling selection ...

-- Gabor

[bassman59]

---

@kurgan wrote:

And component management department kill me if I will use 20 different cap. values.

---

if the design group is overruled by the component management group, the company is destined for failure.

I agree that minimizing the number of different parts on the board is a good thing, but not at the cost of design reliability.

[kurgan]

I haven`t any problem with decoupling and component management.

But using 20+ types of decoupling caps is a stupid anyway.

Design reliability not correlate how much different caps used.

[rcingham]

There is always a compromise between the 'optimal' design, and something that is cheap and easy to manufacture.
If you are the board's designer, it is your job to find a suitable compromise. That is why you are paid some much more than a toilet cleaner.

[kurgan]

There is always a compromise between the 'optimal' design, and something that is cheap and easy to manufacture.
If you are the board's designer, it is your job to find a suitable compromise. That is why you are paid some much more than a toilet cleaner.

Again...

I haven`t any problem with decoupling.

I`m only note that PDN shoul be designed

and not simply copy-pasted from ref. designs.

Done!

[drjohnsmith]

Aint it interesting

I've seen designes that should fail due to rubbush decoupling, but don't

    and boards that have fantastic looking and designed decoupoing, be totaly unreliable.

Ah the joys of being a real engineer, 

   where the rubbe rhits the road is the interesting part 

[rbod]

Interesting read.

I'm not sure if anyone is aware (I'm sure some of you will be). But the cap manufactures (kemet, avx etc..) offer free spice software tailored to their caps. You can add in the caps you think you need and ensure the anti-resonance peaks don't sit at points of interest (like clock fundamentals or their harmonics).

It may give you a little confidence in your design.

Disclaimer: The tools don't take into account mounting and board parasitic. So place the resonance points a little higher than what you need.

Regards

[gszakacs]

Disclaimer: The tools don't take into account mounting and board parasitic. So place the resonance points a little higher than what you need.

These tools don't take account of a lot of things, not the least of which is the load components, which

are typically quite lossy and tend to flatten out those peaks.  It would be very interesting to take one

of these simulations and compare it to a sweep with a frequency generator to see just how much

of a dream world these tools live in...

-- Gabor

[abdullah.shaikh87@gmail.com]

I have refered UG393. It is helpful to me.

But as given in design of Spartan-6 LX150T Development Board (Revesion D) page no.9 , there is a so many decoupling capacitors are connected for VCCINT (+1.2V), as a I understand, each pin of VCCINT would connected to one decoupling capacitor.

And according to UG393 datasheet, for VCCINT there is few capacitors has to be connect like (100uF Qty-02, 4.7uF Qty-03, 0.47uF-06).

So which one should I prefer best one.

This query is same for the VCCAUX,VCCO.

[mcgett]

You should use the current version of UG393.

[secureasm]

Hi,

> You should use the current version of UG393.

Only these capacitors are sufficient for decouplig ?

The doubts increase ...

secureasm