01-23-2013 09:12 PM
I am a graduate student working in the computer vision field. I understand a lot about computer vision algorithms and programming but I am unfortunately not as savvy when it comes to the hardware side of things. I am taking a class in which they want to use Spartan 3e boards in order to learn Verilog. I have messed around with FPGA's via LabVIEW but not with anything like verilog so I am a little familiar with FPGAs themselves and I am very interested in trying to apply it towards a computer vision problem for my thesis that is unrelated to what we are working on in class.
So I have a few things that I need to figure out. The first is what kind of camera would be easiest to interface with a board similar to the Spartan 3e starter board? I just need low resolution for now so 640x480 or something around there would be fine. Black and white is also fine for now but color would be nice at some point (I realize that adds a substantial amount more complexity to getting the video). I don't need a specific model or anything but just some of the genreral qualities to look for such as interface, internal processing, etc.
Then, once a camera is picked out where should I look for information on how to get started on getting images from the camera? I'm not looking for someone to lay out all of the code for me but just point me in the right direction is all. I am very proficient at coding so if I know just the general idea of what needs to happen (especially what hardware should be involved) then I can probably figure out the rest.
Thank you so much for your time and please forgive my ignorance on this issue. I really just don't know where to start and I have tried researching around without much luck.
02-04-2013 12:00 PM
02-19-2013 07:59 AM
Hi.I am facing the same problems..If you have got your answers please help..and what camera did you used finally and how did you interface it with the fpga.I just want some guidance in the right direction..
02-19-2013 10:34 PM
Another thing I don't understand is the following: The Clk125MxC is essentially used as the TX clock for a GMII interface, between the FPGA and an external PHY device. This means that data output lines and the TX_EN signals should be syncrhonized with this clock. However, the way I see it the data are now clocked inside the FPGA with the Clk125MxC but the clock coming out is being delayed by the FF-delay. Isn't that a problem? Is there any way to overcome this?
02-20-2013 12:00 AM
Really? Techno-babble customized SPAM? I don't get it. I wonder if you can call it SPAM if someone actually took the time to manually post it... Oh well.