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eneserdin
Observer
Observer
6,690 Views
Registered: ‎12-25-2007

States of user I/O's for an unconfigured FPGA

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Hi,

 

I am interested in in-system programming of an Spartan 3 FPGA via uBlaze. Do you know the states of the user I/O's of an unconfigured FPGA? Since I will implement a JTAG connection (program loader, prom loader etc.) through FPGA pins which is multiplexed with Platform Cable. However, as the application note says (XAPP482) the TDO pin is not multiplexed and connected directly both to the uBlaze and platform cable connector. I wonder if that TDO of uBlaze creates trouble for me for an unconfigured FPGA.

 

Thanks in advance.

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eteam00
Professor
Professor
8,584 Views
Registered: ‎07-21-2009

Do you know the states of the user I/O's of an unconfigured FPGA?

Typically high impedance or weak pullup to VCCO, depending on state of HSWAPEN pin.

JTAG and configuration pins are not "user I/Os" when unconfigured.

I am interested in in-system programming of an Spartan 3 FPGA via uBlaze.

You understand, of course, that the uBlaze must be running in a second, configured FPGA.  There is no such thing as a uBlaze running in an unconfigured FPGA.

 

- Bob Elkind

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eteam00
Professor
Professor
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Registered: ‎07-21-2009

Do you know the states of the user I/O's of an unconfigured FPGA?

Typically high impedance or weak pullup to VCCO, depending on state of HSWAPEN pin.

JTAG and configuration pins are not "user I/Os" when unconfigured.

I am interested in in-system programming of an Spartan 3 FPGA via uBlaze.

You understand, of course, that the uBlaze must be running in a second, configured FPGA.  There is no such thing as a uBlaze running in an unconfigured FPGA.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

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eneserdin
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Registered: ‎12-25-2007

In the datasheet, it was saying that a high level HSWAP_EN makes the user I/Os "float" !?. That made everything clear, thanks!

 

For the other part I think I have to write things more explanatory. I don't ask the states of the user I/Os while configuration. Think that, there is a PROM and an FPGA on the JTAG chain. When you "first time" power up the board, after the board came from production, FPGA is not configured so does the PROM, and I want to load a PROM file into the PROM, that is the FPGA is bypassed in the Impact S/W. In that case the FPGA is not (being) configured however the JTAG chain is working. In that case the user I/O (namely TDO) that I duplicated on an FPGA pin can make things bad or not? (one of the duplicated net goes to Jtag connector and the other goes to user i/o)

 

If there is something wrong please let me know.

 

Thanks.

 

 

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eteam00
Professor
Professor
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Registered: ‎07-21-2009

In the datasheet, it was saying that a high level HSWAP_EN makes the user I/Os "float" !?. That made everything clear, thanks!

Are you being sarcastic?  In the hardware engineering world the term "floating input" is well understood.  A "floating" pin or net means that it is not being driven - actively or passively.  If the pin or net is connected to a logic gate input, its logic state is indeterminate.

 

Your description is still unclear.

 

If you wish to use a microBlaze to directly program an FPGA, the microBlaze must be resident in an FPGA other than the one which is being programmed.

 

If you wish to use a microBlaze to program a PROM, to load a new FPGA configuration file, this is quite straightforward to implement.  In this manner, a microBlaze can be used to indirectly re-program the same FPGA in which it resides.

 

  • An unconfigured FPGA can be programmed via JTAG (e.g. IMPACT).
  • An unconfigured FPGA can be used to indirectly program a PROM via JTAG (e.g. IMPACT).
  • If the PROM is a JTAG PROM (e.g.  Xilinx Platform Flash), JTAG (including IMPACT) can be used to directly program the PROM.
  • A microBlaze implementing a JTAG controller can be used to directly program a JTAG PROM (e.g. Platform Flash)
  • A configured FPGA may be designed to disable its JTAG port, perhaps to use the JTAG pins for user IO.  In such cases, the configured FPGA may NOT be programmed via JTAG.

Does this answer your question?

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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eneserdin
Observer
Observer
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Registered: ‎12-25-2007

Of course I am not sarcastic. I am only a young engineer whose mother tongue is not English. Additionally in the datasheet it does not say floating input it only says float. Anyway, I do not want to annoy you. My respect to you, the expert designers. Thank you for your invaluable comments.

 

Rearrangement of the question, forget about everything. What is the state of the I/O's of an FPGA when you just power it up (No PROM, no JTAG).

 

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eteam00
Professor
Professor
6,630 Views
Registered: ‎07-21-2009

What is the state of the I/O's of an FPGA when you just power it up (No PROM, no JTAG).

Already asked and answered:

> Do you know the states of the user I/O's of an unconfigured FPGA?

Typically high impedance or weak pullup to VCCO, depending on state of HSWAPEN pin.

JTAG and configuration pins are not "user I/Os" when unconfigured

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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bassman59
Historian
Historian
6,622 Views
Registered: ‎02-25-2008

 


@eneserdin wrote:

 

 

Rearrangement of the question, forget about everything. What is the state of the I/O's of an FPGA when you just power it up (No PROM, no JTAG).

 


This information is IN THE FINE USER GUIDE. Read it.

 

----------------------------Yes, I do this for a living.
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gregmeredith
Xilinx Employee
Xilinx Employee
6,570 Views
Registered: ‎07-30-2007

Just to be clear you can pick between High-Z or pullup by tying the HSWAP pin up or down, and that is right that this is further documented in the config user guide.

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