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Visitor ramanandn
Visitor
4,119 Views
Registered: ‎01-28-2010

Synchronizing clocks

Hello, Need help to figure out how to synch 2 clocks;  not high speed (sub 5 MHz range).. Thanks.
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Scholar austin
Scholar
4,117 Views
Registered: ‎02-27-2008

Re: Synchronizing clocks

r,

 

You have not provided enough information to supply an answer:

 

1.  Where are these clocks?  Where do they come from?  Are you able to adjust them?

 

2.  Are these clocks asynchronous, isochronous, or syntonous?  If you do not know what these terms mean:  go look them up, so you understand them.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor ramanandn
Visitor
4,108 Views
Registered: ‎01-28-2010

Re: Synchronizing clocks

One of the clocks is an input (freq f) to the top module.

 

The other is generated from an external clock (to the top module) of freq 8f & divided by 4 using DCM_SP to get a output clkdv of 2f.

 

I need to synch the f & 2f clocks. No, I couldn't use DCM just to multiply since they fall way below the min input freq of the DCM.

 

I guess that means they're asynchronous.. 

 

Thanks.

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Scholar austin
Scholar
4,097 Views
Registered: ‎02-27-2008

Re: Synchronizing clocks

r,

 

Is there data aligned with the external clock that you need to send into the device (and process), or is there data in the device, which needs to be sent out, and aligned with the external clock?

 

If this is the case (either, or both), that is what a FIFO is used for:  to transfer data from one clock domain, to another.

 

When using a FIFO, there are flags to tell you when data is ready to be read, or written.  When the FIFO is full, it will tell you that it can hold no more data (until someone reads some out the other end).  When the FIFO is empty, you will need to wait until the other side puts something in.

 

 The FIFO in your case, needs to be an asynchronous one, and you will find that either already built into the hardware (V5, V6), or there are "IP cores" in the libraries to do this, or you may wiish to write the HDL code for your own FIFO (although this is not recommended, unless you already know what you are doing).

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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