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Observer urodacus
Observer
2,984 Views
Registered: ‎04-28-2017

Synthesize warning - I need help

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Hello,

 

I'm trying to synthesize a code (working fine on Isim). The fact is I got some problem when I want to synthesize it, here's a part of my code where the warning is :

 

   when S2 => 
	           if (count >= 22 and 28 >= count) then
                  if value_inp = '0' then
                     state <= S3;
                  end if;
              elsif(count <22) then   
                  if value_inp = '0' then
                     state <= S1;
                  end if;
              elsif(count > 28) then 
                 state <= S1;
              end if;
              if rising_edge(clk_inp) then
                 count <= count +1;       
              end if;
  when others => state <= S1;
                 count <="000000000";

   end case;

end process;

detection_outp <= '1' when state = S3 else '0';
count_value_outp <= count when state = S3 else "000000000";

 

The "value_inp" is a STD_LOGIC input, its value is '1' when entering S2,

count is a STD_LOGIC_VECTOR signal (9 bits), I use him later in the code.

detection is a STD_LOGIC output

count_value_outp is here because I need to know (for other functions) what was the counter value after detection

 

I can't show all the code, let's say that in S3 nothing special is happening and that's a state where the state machine is going when everything is over (in fact, it's S10 but even when i comment S3 to S10 i got the warnings :( )

 

My process is declared like that : process(clk_inp,value_inp, enable_inp)

My states : type state_t is (S1,S2,S3,S4,S5,S6,S7,S8,S9,S10);

At the end I got : 

 

My warning messages are :

 

"WARNING:Xst:737 - Found 1-bit latch for signal <state<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <state<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <state<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <state<0>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems."

""WARNING:Xst:1293 - FF/Latch <state_2> has a constant value of 0 in block <SM_detection_preambule>. This FF/Latch will be trimmed during the optimization process.""

 

Somebody got an idea?

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1 Solution

Accepted Solutions
Moderator
Moderator
5,458 Views
Registered: ‎11-09-2015

Re: Synthesize warning - I need help

Jump to solution

HI @urodacus,

 

You need to specify an else condition and give a value to state for each if (in which you give a value to state)

 

                 if value_inp = '0' then
                     state <= S3;
else
state <= S2 end if;

 

 

 Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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4 Replies
Moderator
Moderator
5,459 Views
Registered: ‎11-09-2015

Re: Synthesize warning - I need help

Jump to solution

HI @urodacus,

 

You need to specify an else condition and give a value to state for each if (in which you give a value to state)

 

                 if value_inp = '0' then
                     state <= S3;
else
state <= S2 end if;

 

 

 Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

Observer urodacus
Observer
2,964 Views
Registered: ‎04-28-2017

Re: Synthesize warning - I need help

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@florentw wrote:

HI @urodacus,

 

You need to specify an else condition and give a value to state for each if (in which you give a value to state)

 



Thanks for the tip ! It helped, I just had to add tons of "else" statement :)

 

Another thing now, I got 2 warnings like :

"WARNING:Xst:2170 - Unit SM_detection_preambule : the following signal(s) form a combinatorial loop:" with some signals after

 

and

 

"WARNING:HDLCompiler:92 - "C:\Users\erwan.barret\Desktop\FPGA\CarteADSB_update\ReceptionADSB\SM_detection_preambule.vhd" Line 233: count should be on the sensitivity list of the process"

 

Should I be worried if the simulation is working just fine?

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Moderator
Moderator
2,954 Views
Registered: ‎11-09-2015

Re: Synthesize warning - I need help

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Hi @urodacus,

 

It is just warning. You can choose to ignore them. If your design is working in both behavioral and post-implementation simulations then it should be fine.

 

However you should try to have as little warning as possible.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer urodacus
Observer
2,945 Views
Registered: ‎04-28-2017

Re: Synthesize warning - I need help

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Ok thanks,

 

I think the warning about the process sensitivity signals is because i'm checking the count value in the states (but only on falling edge and rising edge of another signal so... It doesn't matter if it's in the process signals).

 

I wanted to avoid the others warning but I don't know where it comes from.

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