04-19-2017 07:19 AM
I am using Atlys Spartan 6 FPGA development board. I have to combine XAPP495 with external memory interface. When I combine the DDR2 interface example code available here with XAPP495, I get the following error:
Too many comps of type "PLL_ADV" found to fit this device.
The design is too large to fit the device.
I am unable to find any "PLL_ADV" in XAPP495 verilog files. Please guide how should I remove this error. I have consulted Hierarchical Design Methodology Guide but cannot find to remove the error. Thank you.
04-19-2017 07:27 AM
Put simply, you are using more PLLs than the available number in the device. I won't do your homework, but both designs are likely using some PLLs and that just amount to too many of them.
04-19-2017 08:23 AM
The PLL_ADV cell is used whenever a PLL is instantiated, whether the actual instantiation is of a PLL_ADV or a PLL_BASE.
So if the number of PLL_ADV + PLL_BASE instantiations (including generated loops) exceeds the number of PLL_ADV cells on the die, which for the LX45 is 4, then you will get this error.
04-23-2017 05:22 AM
Please check whether any of the below link documents information helpful to debug the issue?