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Visitor
Visitor
3,058 Views
Registered: ‎08-12-2016

Too many comps of type "PLL_ADV" found to fit this device

Hi,

 

I am using Atlys Spartan 6 FPGA development board. I have to combine XAPP495 with external memory interface. When I combine the DDR2 interface example code available here with XAPP495, I get the following error:

Too many comps of type "PLL_ADV" found to fit this device.

The design is too large to fit the device.

 

I am unable to find any "PLL_ADV" in XAPP495 verilog files. Please guide how should I remove this error. I have consulted Hierarchical Design Methodology Guide but cannot find to remove the error. Thank you. 

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Xilinx Employee
Xilinx Employee
3,050 Views
Registered: ‎11-03-2016

Hi,

Put simply, you are using more PLLs than the available number in the device. I won't do your homework, but both designs are likely using some PLLs and that just amount to too many of them.

 

Regards,

YL

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Guide
Guide
3,039 Views
Registered: ‎01-23-2009

The PLL_ADV cell is used whenever a PLL is instantiated, whether the actual instantiation is of a PLL_ADV or a PLL_BASE.

 

So if the number of PLL_ADV + PLL_BASE instantiations (including generated loops) exceeds the number of PLL_ADV cells on the die, which for the LX45 is 4, then you will get this error.

 

Avrum

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Xilinx Employee
Xilinx Employee
2,971 Views
Registered: ‎08-01-2012

Please check whether any of the below link documents information helpful to debug the issue? 

https://www.xilinx.com/support/answers/39627.html

https://www.xilinx.com/support/answers/44714.html

https://www.xilinx.com/support/answers/61934.html

https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/spartan6_hdl.pdf 

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