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sarno
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Registered: ‎01-23-2013

Tristate issue on spartan-3AN - XST : 2042

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Hi,

 

I am trying to command a stand alone memory with a spartan-3AN board, for that I send the data, signals and addresses  on the Hirose expansion port.

I simulate the design with ISIM and everything is working fine as far as i can see for i cannot simulate the memory itself (I have a simulation model but ISIM cannot deal with 1Mb signal).

I tested it too, with a logic analyser i can see that the signals, addresses and writing data are right and that the timing is good too but the reading is not right.

 

My guess is that it has something to do with the bidirection data bus, I understood that internal tristate are no longer available on spartan-3, but i cannot see anyway not to use it and i am not sure the pull-up which are remplacing it can do the job.

 

Here is the tristate code

 

// tristate.v
// ----------------------------------------------------
//	input => to the FPGA
//	output => to the MRAM
// ----------------------------------------------------

module tristate(
	mram_dq_i,
	mram_dq_o,
	mram_dq_io,
	mram_W_o
	);
	
input[7:0] mram_dq_o;
output[7:0] mram_dq_i;
input mram_W_o;
inout [7:0] mram_dq_io; 

wire [7:0] mram_dq_i;
wire mram_W_o;
wire [7:0] mram_dq_io;
wire [7:0] mram_dq_o;

reg [7:0] mram_input_s;
reg [7:0] mram_output_s;

wire mram_W_inv_s;

assign mram_dq_i = mram_input_s;
assign mram_W_inv_s = ~mram_W_o;

assign mram_dq_io = (mram_W_inv_s) ? mram_output_s : {8{1'bz}};

always@(*)
begin
  mram_input_s <= mram_dq_io;
  mram_output_s <= mram_dq_o;
end

endmodule

 

Assuming the memory is functionning (i tried 2 to be sure) and given that the right signals and address is sent at the right timing, it just left the data bus (dq) and this internal tristate warning.

 

Is there a way not to have bidir without tristate ?

 

Thanks

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hgleamon1
Teacher
Teacher
7,861 Views
Registered: ‎11-14-2011

You haven't mentioned what version of the tools you are using but I recommend reading the Spartan 3 Libraries Guide for HDL (UG607). The 13.3 version (tools version I have installed) can be found here.

 

Here the IOBUF primitive is explained, as well as how to instantiate it (Verilog example available), although I imagine that it is simple to infer.

 

The OBUFT primitive is still there but if you want bidirectional I/O, rather than just a tristateable output, I would use the IOBUF.

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle

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bassman59
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Registered: ‎02-25-2008

Is there a way not to have bidir without tristate ?

 

No. Unless you have separate input and output buses.

----------------------------Yes, I do this for a living.
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hgleamon1
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Registered: ‎11-14-2011

@bassman59 wrote:

Is there a way not to have bidir without tristate ?

 

No. Unless you have separate input and output buses.


Which, in my opinion, is exactly the right way to approach bidirectional communications between internal modules or carry a bidirectional bus up and down a hierarchical structure. For the latter case, leave the tristate instantiaton at the top level and thereby completely remove any possibility of internal tristates and their replacement by logic.

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle
sarno
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6,194 Views
Registered: ‎01-23-2013

Thanks for your answers.

Are you meaning that if it is impossible for Spartan 3AN to have internal tristate (BUFT), it would be possible to have output tristate (OBUFT)?

Because as you said there are no way to have bidirectionnal without tristate, so there must be a way for the fpga to deal with it.

 

Putting the tristate verilog code directly in the top will have xst make OBUFT instead of BUFT ?

 

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hgleamon1
Teacher
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Registered: ‎11-14-2011

You haven't mentioned what version of the tools you are using but I recommend reading the Spartan 3 Libraries Guide for HDL (UG607). The 13.3 version (tools version I have installed) can be found here.

 

Here the IOBUF primitive is explained, as well as how to instantiate it (Verilog example available), although I imagine that it is simple to infer.

 

The OBUFT primitive is still there but if you want bidirectional I/O, rather than just a tristateable output, I would use the IOBUF.

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle

View solution in original post

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sarno
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Registered: ‎01-23-2013

That might actually solve my problem, i'll try that.

 

Thanks !

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bassman59
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Registered: ‎02-25-2008

@sarno wrote:

Thanks for your answers.

Are you meaning that if it is impossible for Spartan 3AN to have internal tristate (BUFT), it would be possible to have output tristate (OBUFT)?

 


It is definitely possible to have bidirectional FPGA pins on any of the Xilinx FPGAs. And necessarily a bidirectional pin must be tristate-able. I think the primitive is IOBUFT, but I just write VHDL that describes the behavior and the tools do the right thing.

 

And, again, there are NO tristate/bidirectional nets within the FPGA.

----------------------------Yes, I do this for a living.
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