I need your help for generation a DDR
SDRAM-controler core for the board "Memec Spartan-3 MB". The FPGA on
the board is a Spartan-3 XC3S1500 in the package FG676 with speedgrade
of -4. The DDR-SDRAM on the board is a Micron MT46V16M16FG-75 16Mx16.
I tried to generate a design with the tool MIG 1.72 with the follwing parameters: datawith = 16, frequency = 100MHz, CAS = 2, burstlenght = 2, bursttype=sequential, use DCM, selected banks=bank5 and bank4.
I chose the right FPGA and the right DDR SDRAM and I entered the reserved Pins via ucf-file from the board. My
problem is that the pins for the board are already predefined by Memec
and the MIG-Tool takes completly different Pins for the design of the
controler. Now I'm afraid to correct the pins in the ucf-file in the
way they should be selected for the Memec-board, because I think that
time delays will change and other time or path violences will occur, so
that for example the read capture does not work correctly. Can you
support me to generate the core for the described board? I'm very glad
about every useful hint that Xilinx can give.
Thank you very much and looking forward to receive an answer.