We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor vramamoorthy
Registered: ‎12-08-2010

Two Strange Problems with ISE 12.2 (nt) M.63c

I am having strange problems with ISE 12.2.


(1) It seems to read UCF files but all the input nodes are disconnected. In other words, after generating programming file successfully,  if I open Pinout Report file, I find that all input nodes are unused though they are all there in the UCF file. As expected, the input pins do not respond to input signals after the FPGA has been programmed through Impact. The output nodes are seen in the Pinout Report as used. However FPGA does not work.


(2) If I open PlanAhead I/O planning (pre-synthesis) under ISE, I can see all nodes and pins found in the UCF file. However I am unable to save the design as the menu FILE > SAVE DESIGN is greyed out. I can only export the files to another PlanAhead folder and ISE does not seem to read this folder at all. I have asked for help in a previous posting regarding PlanAhead.


I suspect some project setting - but don't know which.


Please Help.




0 Kudos
3 Replies
Registered: ‎07-30-2007

Re: Two Strange Problems with ISE 12.2 (nt) M.63c

 Hi Victor,


It is normal for the plan ahead "save" to be greyed out until you make a change.  If the Physical I/O shows the right connections you're good to go.


Inputs can go away during implementation if they are optimized out of the design.  For them to be kept they must drive an output!   I did a test of this to be sure and I get a message in map like " MAPLIB:701 signal connected to top level port CLKN has been removed."  After that the CLKN signal which shows in planahead as connected does not show up in the pin out report. 


You could consider the schematic viewer to try to make sure the design is synthesized the way you expect. (Where have I heard this before:smileyhappy: )




Don't forget to reply, kudo, and accept as solution

Newbie cemilaryan
Registered: ‎10-24-2011

Re: Two Strange Problems with ISE 12.2 (nt) M.63c



I'm having problem with finding Pad Report or Pinout Report.

I went to Place&Rout Properties to select Multip Pass Place&Route (as per Help instruction for find this Report),

still there is no such an option in that Properties Box.


Please help me how can I have access to this Pad Report.

I'm using ISE 11.1.




Tags (1)
0 Kudos
Xilinx Employee
Xilinx Employee
Registered: ‎08-02-2007

Re: Two Strange Problems with ISE 12.2 (nt) M.63c



You'll want to look at the Design Summary Tab.  If you've closed this, you can simply relaunch it from project-> design summary/reports.  From there I dont believe pad is on by default, but there is a pinout report which should contain what you are looking for.  If you want a pad generated. you can hit the little icon on the left of the frame that has a bunch of checks on it, and then enable pad report generation.


Hope this helps,

0 Kudos