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Newbie reedbement
Newbie
5,532 Views
Registered: ‎06-08-2009

Two phase clock gives warning: Route - CLK Net:FX2_CLK0_BUFGP may have excessive skew because...

My design drives an external SDRAM which is clocked on the oposite phase from a controlling state machine. With clock inversion: :

 

assign SDRAM_CLK = ~FX2_CLK;
 

I get the following error:

Route - CLK Net:FX2_CLK0_BUFGP may have excessive skew because 0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.

 

With no clock inversion:

assign SDRAM_CLK = FX2_CLK;

I have no warnings. I've tried using a BUFG as suggested in some other posts, but get similar results:

 

BUFG bufg_inst(FX2_CLK1, ~FX2_CLK0);

 

I have the feeling that I'm doing something fundamentally wrong with my clock configuration. It doesn't seem as though I should have to resort to a DCM to get a two phase clock  on this relatively slow (48MHz) design. What I would like is something like the following:

 

two global clocks 180 degrees out of phase

 

 

But I'm not sure how to specify this unambiguously. Is there an inverting version of BUFG? Is there an easy way to browse the architecture specific elements (like BUFG) from inside the ISE?  I'm using verilog as my HDL.

TIA for any suggestions. -Reed

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2 Replies
Historian
Historian
5,519 Views
Registered: ‎02-25-2008

Re: Two phase clock gives warning: Route - CLK Net:FX2_CLK0_BUFGP may have excessive skew because...


reedbement wrote:

My design drives an external SDRAM which is clocked on the oposite phase from a controlling state machine. With clock inversion: :

 

assign SDRAM_CLK = ~FX2_CLK;
 

I get the following error:

Route - CLK Net:FX2_CLK0_BUFGP may have excessive skew because 0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.

 

With no clock inversion:

assign SDRAM_CLK = FX2_CLK;

I have no warnings. I've tried using a BUFG as suggested in some other posts, but get similar results:

 

BUFG bufg_inst(FX2_CLK1, ~FX2_CLK0);

 

I have the feeling that I'm doing something fundamentally wrong with my clock configuration. It doesn't seem as though I should have to resort to a DCM to get a two phase clock  on this relatively slow (48MHz) design. What I would like is something like the following:

 

two global clocks 180 degrees out of phase

 

 

But I'm not sure how to specify this unambiguously. Is there an inverting version of BUFG? Is there an easy way to browse the architecture specific elements (like BUFG) from inside the ISE?  I'm using verilog as my HDL.

TIA for any suggestions. -Reed


 

Those warnings result from your use of the clock for both clocking (your state machine's flip-flops, etc) as well as the inverter and output pin.

 

Use a DCM for your clock inversion. Drive the inverted (CLK180) DCM output to the clock output pin. Use the CLK0 DCM output for your state machine logic.

 

-a

Message Edited by bassman59 on 06-08-2009 02:18 PM
----------------------------Yes, I do this for a living.
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Voyager
Voyager
5,503 Views
Registered: ‎08-30-2007

Re: Two phase clock gives warning: Route - CLK Net:FX2_CLK0_BUFGP may have excessive skew because...

It looks like you are trying to directly drive the internal clock to an output pad (with inversion), correct?

 

Xilinx FPGAs don't have a simple path to go from the internal global clock to an output pad.  The best

way to forward a clock to the outside world is to use the DDR flop that's in the IOB.   This controls

the clock delays and avoids the global-clock routing restrictions.

 

Try this instantiation:

ODDR(

  .Q  (SDRAM_CLK),

  .C  (FX2_CLK),

  .CE (1'b1),

  .R  (1'b0),

  .S  (1'b0),

  .D1 (1'b0),

  .D0 (1'b1)

);

 This will invert the input clock and forward it to your output pin.  If you wanted to forward the

clock without inversion, you'd just swap the D0/D1 values.

 

I Hope this helps!

 

 

John Providenza


 

 

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