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Visitor m.rescati
Visitor
9,311 Views
Registered: ‎05-06-2016

UCF clock frequencies

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Hi,

I'm new to fpga world. I spent some time trying to reduce the clock frequencies of my fpga a spartan 6 xc6slx45fgg484-2. I put in the ucf contraints file this lines:

Net "clk_out" LOC="Y11";

NET "clk_out" TNM_NET = "clk_out";

TIMESPEC "TS_clk_out"= PERIOD "clk_out" 40 ns;

 

if i cut the first line the clock totally disappear and the fpga simply don't give out any output. if i leave the first line he simply put out the default clock (50 MHz for Y11 and 100 for AB13).

I tried to use clock wizards and read all the forums e some guide on the internet but the results are always the same.

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1 Solution

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Moderator
Moderator
17,675 Views
Registered: ‎07-01-2015

Re: UCF clock frequencies

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Hi @m.rescati,

 

Do you mean changing the clock period in 3rd line not helping?

If you change the clock period then frequency for which design will be analysed will change but on board the freauency is same as the oscillator frequency.

 

Thanks,
Arpan

Thanks,
Arpan
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12 Replies
Moderator
Moderator
17,676 Views
Registered: ‎07-01-2015

Re: UCF clock frequencies

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Hi @m.rescati,

 

Do you mean changing the clock period in 3rd line not helping?

If you change the clock period then frequency for which design will be analysed will change but on board the freauency is same as the oscillator frequency.

 

Thanks,
Arpan

Thanks,
Arpan
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Visitor m.rescati
Visitor
9,279 Views
Registered: ‎05-06-2016

Re: UCF clock frequencies

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Thank you Arpan, I think I got the answer I was looking for. What's the right way to change the oscillator frequency?

I'm asking too much now, but someone can really some my week end.

my teacher thinks that the problem with the signal integrity was due to the high frequency we gave to the Pll. So I would like to know where to look for:

1 Pll-clock managing in general

2 how can I model the signal integrity (I had problems with the ibis file, really don't know how to use them.)

i prefer at this point som thing more academic like books rather than fpga manual. I'm asking too much now, but really it's difficult to study new fields in so few time alone. Thank you 

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Moderator
Moderator
9,277 Views
Registered: ‎07-01-2015

Re: UCF clock frequencies

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Hi @m.rescati,

 

For IBIS model please go through:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/pp_p_process_generate_ibis_model.htm

http://www.xilinx.com/products/design_resources/signal_integrity/si_whyibis.htm

 

 

Thanks,
Arpan

 

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Thanks,
Arpan
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Visitor m.rescati
Visitor
9,269 Views
Registered: ‎05-06-2016

Re: UCF clock frequencies

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Thank you!
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Historian
Historian
9,240 Views
Registered: ‎01-23-2009

Re: UCF clock frequencies

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It's a little unclear what you are asking for.

 

Are you trying to change the frequency of the clock through constraints? If so, then you can't.

 

Constraints merely describe the clock that exists in the system (i.e. board) to the tools. They neither create them, nor do they modify them. In your system (on your board) there are two oscillators one which is 50MHz connected to one pin of the FPGA and one which is 100MHz connected to another pin. This is physically what you have on your board, and hence what you have available to the FPGA.

 

If you need some other frequency inside the FPGA, then you need to use the clock management cells in the FPGA to generate a new clock. In the Virtex-5, there are DCMs and PLLs. You use the clock wizard to tell it "I have a 50MHz clock, and I want you to generate a 25MHz clock from that". The wizard will then create the proper attributes for the DCM or PLL to convert a 50MHz clock to a 25MHz clock.

 

None of this has anything to do with constraints. Your constraints are telling the tool:

  1) I am connecting the signal on the board that is connected to pin Y11 to the input port of my RTL design called "clk_out"

     - (and its a bit puzzling as to why you are calling "clk_out" when it is an input)

  2) (this is a bit esoteric, but) I am creating a Time Group for all clocked elements clocked by the net "clk_out", and I am calling the group "clk_out"

  3) The clock on for the Time Group "clk_out" has a 40ns period

      - this is incorrect - on your board, that pin is connected to a 50MHz oscillator, so the period is 20ns

 

Avrum

Visitor m.rescati
Visitor
9,163 Views
Registered: ‎05-06-2016

Re: UCF clock frequencies

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Yes, that's what is was trying to do. I still have no idea how to use the clock manager and the clock wizard. Can someone help? Thank you both for the answers, I'm a newb of the fpga world and so is all my group so I don't know where to start for everything. I read I can give the clock from the outside, but still I don't know how to do it the right way. 

A last question: does somebody know if I can find the schematic for the output buffer? I don't think is possible but if I could be able to find it then my work could be great! Thank you again everybody 

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Moderator
Moderator
9,161 Views
Registered: ‎07-01-2015

Re: UCF clock frequencies

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Hi @m.rescati,

 

Go to IP catalog-> Clock wizard.

Double click on the same. You will get an option to set the MMCM output frequency.

Give input frequency as your oscillator frequency and set the Divider and multiplier values to obtain desired output frequencies.

Thanks,
Arpan
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Visitor m.rescati
Visitor
9,157 Views
Registered: ‎05-06-2016

Re: UCF clock frequencies

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I don't know how to show how grateful I am! 

Arpan and avrum probably just saved me a week of desperation. Thank you to both!

If somebody else have some tips or link useful I could use some help anyhow!

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Moderator
Moderator
9,148 Views
Registered: ‎07-01-2015

Re: UCF clock frequencies

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Hi @m.rescati,

 

As you are using Spartan-6 please go through page-69 of following link for DCM
http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

Thanks,
Arpan
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Visitor m.rescati
Visitor
7,535 Views
Registered: ‎05-06-2016

Re: UCF clock frequencies

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I'm still blocked there. When I try to run the implementation after I set the clock wizards a message appear that say: "could not find module 'clk_wiz_v3_6_0" the ucf file clk_wiz will not be read.

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Visitor m.rescati
Visitor
7,459 Views
Registered: ‎05-06-2016

Re: UCF clock frequencies

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Ok, I was at last be able to use the digital clock manager. Still I have my problems if I want to give the clock from the outside. I put in the ucf a pin from where i would like to give the clock and error messages come out. I must use the internal oscillator as the only clock source for the fpga?

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Moderator
Moderator
7,439 Views
Registered: ‎07-01-2015

Re: UCF clock frequencies

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Hi @m.rescati,

 

Are you doing the following:

1. Declare oscillator clock as clock in UCF.

2.Put oscillator clock as input to DCM and connect output of DCM to logic?

Thanks,
Arpan
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