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Newbie hapfel
Newbie
2,616 Views
Registered: ‎07-11-2017

Unable to generate Spartan-II .mcs files with ISE 10.1 anymore

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Dear board,

 

I've got problems generation "correct" .mcs-files with a ISE 10.1 for an spartan-II XC2S100PQG208.

It's sort of a historical design with an old code base. So, the old .mcs file loads fine (into an ATI17LV010 via parallel port) and the system works. But we've found a bug so I had to to reinstall the ISE again.

Compiling and generating the .mcs works just fine (albeit the ISE crashes quite often), but the FPGA doesn't accept the code. So I eventually looked into the bit code:

 

The new .mcs generated starts with

FFFFFFFF AA995566 30008001 0000000007 3E

.. as it should re https://www.xilinx.com/support/documentation/application_notes/xapp176.pdf

 

but the old one starts with

FFFFFFFF 5599AA66 0C000180 00000000E0 0C

and it's the working one?!

 

Chip marking is XC2S100PQG208

 

Anybody knows whats happening? Or may point me into the right direction?


Thank you sincerely


H. Apfel

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Xilinx Employee
Xilinx Employee
4,671 Views
Registered: ‎09-05-2007

Re: Unable to generate Spartan-II .mcs files with ISE 10.1 anymore

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You need to play with the bit swapping option (or whatever it is called). It's the option that reverses the bits within each byte.

 

At the start of the image you can see the SYNC word that begins 'AA995566'. Let's look at the first two bytes...

 

AA 99 = 10101010   10011001

 

Reverse the bits of each byte (e.g. swap bit0 with bit7, bit1 with bit6 etc)

 

55 99 = 01010101   10011001

 

It's all to do which what sort or memory you are using and how bytes are serialised starting LSB or MSB first. Usual story, if there are two ways to do something then we always pick the wrong way first :-)

Ken Chapman
Principal Engineer, Xilinx UK
5 Replies
Scholar pratham
Scholar
2,600 Views
Registered: ‎06-05-2013

Re: Unable to generate Spartan-II .mcs files with ISE 10.1 anymore

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@hapfel What do you mean by "FPGA doesn't accept the code. So I eventually looked into the bit code:"

Are you facing any issues while programming this new mcs? if yes, share the log files.

 

Also,share the steps you had taken to generate the new mcs and compare it with older mcs.

What is the configuration mode are you using?

-Pratham

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Xilinx Employee
Xilinx Employee
4,672 Views
Registered: ‎09-05-2007

Re: Unable to generate Spartan-II .mcs files with ISE 10.1 anymore

Jump to solution

You need to play with the bit swapping option (or whatever it is called). It's the option that reverses the bits within each byte.

 

At the start of the image you can see the SYNC word that begins 'AA995566'. Let's look at the first two bytes...

 

AA 99 = 10101010   10011001

 

Reverse the bits of each byte (e.g. swap bit0 with bit7, bit1 with bit6 etc)

 

55 99 = 01010101   10011001

 

It's all to do which what sort or memory you are using and how bytes are serialised starting LSB or MSB first. Usual story, if there are two ways to do something then we always pick the wrong way first :-)

Ken Chapman
Principal Engineer, Xilinx UK
Newbie hapfel
Newbie
2,593 Views
Registered: ‎07-11-2017

Re: Unable to generate Spartan-II .mcs files with ISE 10.1 anymore

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Hello Pratham,

I don't have any problems generating the .mcs code. In fact the code generated looks exactly as it should look (Byte positions, byte order) according to the XILINX specs I mentioned above.So everthing looks fine. Writing into the serial configuration EEPROM on board - again no problem.

But the Spartan refuses to accept the bitstream: DONE stays low and the CPU in the system doesn't find the FPGA (there is a magic at a specific address just for those cases).

 

The FPGA accepts the old .mcs file (written by the same hardware into the same system). But the old file got the byte order wrong (no, not simply big vs. little endian - competely mangled) and starts to get completely wierd afterwards a few longwords if compared to the official XILINX documentation (link see my first post).

 

So I'm at a complete loss:

- the new ISE setup seems to generate the correct bitstream according to spec (see first post) but the FPGA doesn't accept it.

- the old (late) ISE somehow generated a bitstream that wasn't according to spec (see first post) but the FPGA accepts it, pulls DONE high and the CPU within the system "finds" the FPGA.

 

Thats where I admit I'm out of ideas. I did compile the former .mcs on an ISE 10.1 on Win XP, but when I installed the ISE 10.1 on an old Win XP system again it produced the same .mcs (as it should) with the same header to spec as the new installation on a Linux machine did which - unsurprisingly - was rejected by the FPGA as well.

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Newbie hapfel
Newbie
2,591 Views
Registered: ‎07-11-2017

Re: Unable to generate Spartan-II .mcs files with ISE 10.1 anymore

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chapman, d*mmit, you're probably absolutely right!

 

Will try right now

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Newbie hapfel
Newbie
2,584 Views
Registered: ‎07-11-2017

Re: Unable to generate Spartan-II .mcs files with ISE 10.1 anymore

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Jepp, that's it!
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