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Newbie
Newbie
9,947 Views
Registered: ‎09-10-2007

Unknown errors / warnings from ISE

I am trying to implement a shift register using the following construction:
 
 reg [15: 0] output_temp;
      repeat(16) begin
       output_temp[0] <= input_temp[0];          // save a bit
       output_temp <= output_temp << 1;       // next output bit
       input_temp <= input_temp >> 2;           // next input bit
     end
 
I get this error message for all 16 bits of output_temp:
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <output_temp_15> has a constant value of 0 in block <rcvr>.
 
I can't find an explanation for this warning anywhere in the Xilinx web search or elsewhere. Any ideas on what to do next?
 
 
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Xilinx Employee
Xilinx Employee
9,941 Views
Registered: ‎08-15-2007

Xilinx has verilog examples for shift register inference in the XST User Guide:
Typically, you will get these types of warnings if the output of the a FF is not changing (it is a constant).  Have you looked at the logic connected to input_temp, is this changing?  Is something else upstream causing input_temp to get optimized to 0, so output_temp is also 0?
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Newbie
Newbie
9,937 Views
Registered: ‎09-10-2007

Thanks. I figured it had to be something like that. I'm still learning.
 
 
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