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06-21-2011 03:30 AM - edited 06-21-2011 04:32 AM
Hello,
I an working on a small design based on the XC6SLX75 in the FGG484 package. Two of my IO banks are completely unused and I am wondering what to do with their supply voltages: leave them unconnected, pull to GND or supply normally?
I found in UG385 (Spartan-6 FPGA Packaging and Pinouts) that I can leave VBATT, VFS and RFUSE unconnected but pulling to GND is recommended. And DS162 (Spartan-6 FPGA Data Sheet: DC and Switching Characteristics) specifies that configuration data is retained even for VCCO_# going to 0V. But does the chip work if they are 0V? In my design, this concerns VCCO_0 and VCCO_3.
Connection details:
TCK, TDI, TDO, TMS : VCCAUX : JTAG
DONE, INIT_B, M0, M1, PROGRAM_B : VCCO_2 : Configuration
DOUT : VCCO_1 : Configuration + SPI
CCLK, DIN : VCCO_2 : Configuration + SPI
GCLK0, IO_2 : VCCO_2 : User circuit
On a related note: does power consumption on VCCO_# scale with connected pins? Then I need nearly nothing for VCCO_1.
Thank you for any comments,
Olaf
06-21-2011 07:43 AM
o,
Unused IO banks draw less thasn 2 mA. Connect them to any convenient power supply. 1.2v, 1.5v, 1.8v, 2.5v, etc. Really does not matter, though the lowest voltage means also the lowest current,
The IO protection ESD structures are designed to work while powered (best protection). Even though these pins are not used, they still might get zapped by someone touching them (in test, or some other way).
06-21-2011 03:43 AM - edited 06-21-2011 03:45 AM
I don't work for Xilinx, but I would assume that all power supply pins need to be connected. Why would you avoid connecting any of the power supply pins on the device?
For each of the VCCO_x and VCCAUX supplies, what voltages are you using?
-- Bob Elkind
06-21-2011 04:36 AM
Hello,
I am mainly concerned by power usage: if the usage does not scale linearly with conencted pins but has an offset, then powering banks when I don't have to is a waste.
I planned to use the following settings:
VCCINT = 1.2V
VCCAUX = 2.5V
VCCO_1 = 2.5V
VCCO_2 = 2.5V
Thanks for reading,
Olaf
06-21-2011 04:42 AM
I should say that I am also still considering
VCCO_1 = 1.8V
VCCO_2 = 1.8V
as a low power option (needs an additional voltage rail, though.
06-21-2011 07:43 AM
o,
Unused IO banks draw less thasn 2 mA. Connect them to any convenient power supply. 1.2v, 1.5v, 1.8v, 2.5v, etc. Really does not matter, though the lowest voltage means also the lowest current,
The IO protection ESD structures are designed to work while powered (best protection). Even though these pins are not used, they still might get zapped by someone touching them (in test, or some other way).
06-21-2011 09:36 AM
Hello,
and thanks to both eteam00 and austin.lesea for the reply. I will probably connect VCCINT to my unused banks (VCCO_0 and VCCO_3).
Thanks again,
Olaf
06-21-2011 10:42 AM
I don't know if this is still true,
and I appologies to hyjacking this thread,
but it could be appropreate to this design
but one used to connect unused IO pins to Gnd,
and assign the pins to ground in the code,
to decrease the amount of ground bounce,
Its a while since I have had any free IO pins,
but was wondering if this is still the way to do things.
Austin over to you
06-21-2011 11:02 AM
06-21-2011 11:29 AM
Ta
02-18-2016 04:04 AM
Hello.
Can I connect VCCO pins of unused and NC banks to GND on VIRTEX-5?
02-18-2016 06:49 AM
Read my answer. (Second post, after the first, in this thread).
02-21-2016 06:03 AM
Before asking this question, I did.
And Your answer doesn’t say nothing about GND.
Some people are talking that I can connect unused IO pins to GND.
But if VCCO, of those IO pins, is connected to some voltage, then, since my "HSWAPEN" is connected to GND, pull up resistors will be enabled during configuration, and all those unused IO pins will draw current, since they are connected to GND. I don't want that. If I connect VCCO to GND also, there should be no high current flow during configuration.
You are talking about ESD protection. But if all unused IO pins and VCCO will be routed to GND, then, what? Maybe I don't know something, but, I think GND is better ESD protection. Better than any diode, what is inside of FPGA.
UG195 says "Without a package migration requirement, VCCO pins in unbonded banks can be left unconnected or tied to a common supply (VCCO or ground)."
But I can't find any information regarding bonded, but unused banks.
Only what "Absolute Maximum Ratings" says. It says "VCCO Output drivers supply voltage relative to GND –0.5 to 3.75 V", so GND (0v) should be ok?
Best Regards
02-21-2016 08:18 AM
Yes,
Ground on Vcco is allowed excepting the bank used for configuration (that is required for POR). It is recommended though to tie to any other proper voltage Vcco.