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Visitor exys
Registered: ‎09-21-2009

Usage of outer layers for Spartan-6 DDR DRAM routing.

The Spartan-6 Memory Controller User Guide UG388 v1.1 page 84 at the “General Guidelines”, the first point says “Only internal PCB layers should be used to route memory interface signals between the FPGA and memory devices”. I have done DDR2 PCB design before and have used the two outer layers successfully. Is there a specific reason for why the outer layers cannot be used for memory routing with the Spartan-6?
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Xilinx Employee
Xilinx Employee
Registered: ‎10-23-2007

Re: Usage of outer layers for Spartan-6 DDR DRAM routing.

I think UG388 is too restrictive here.  As long as you have controlled impedance and minimize the number of vias it should be okay.  IBIS simulation is the way to check.  Ideally you route through the via at the package ball with a trace on one plane to the via at the ball of the memory device.  If that is on an outer layer, it should be fine.  There are other reasons you might wish to use the inner layers such as manufacturing rules or EMI, but that is up to the system designer and shouldn't affect memory interface performance.  You should open a case on this and see if they agree and if the UG needs to be updated.
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Observer perica
Registered: ‎05-18-2008

Re: Usage of outer layers for Spartan-6 DDR DRAM routing.

I don’t know exactly why Xilinx suggest using only inner layers (I suppose they don’t want to bother with questions that might arise from various users…).


Using outer layers is quite OK as long as you are aware of signal speed at the outer PCB layer. As we all know voltage signal reach the speed of light. But speed of light isn’t the constant in all medium. Speed of light in inner layers is smaller compared to outer layers, that is because in inner layer the conductor is surrounded by dielectric from both sides. At the outer layer from one side it is the same dielectric as in inner layer but at the other side the dielectric is different.




Message Edited by perica on 09-24-2009 03:53 AM
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