01-05-2014 08:24 AM
I have coded a VHDL video synthesis IP for testing. It generates Data, H/V sync, H/V blank, DE and Fsync. I have tested it using ADV7511 hdmi controller successfully.
I'm trying to make use of Xilinx VDMA in a microblaze environment.
MY IP > v_vid_in_axi4s > VDMA > v_axi4s_vid_out > HDMI
My generated Fsync (fs) gets high for a single pixel clock during the last pixel in frame, so its falling edge marks the new frame, is this ok? Please check the attached chipscope snapshot.
In the image below, my IP is initially trying to write pixel data which cause errors, then a new frame starts, marked by "fs". This triggers the s2mm_intr which never gets down. We then see a vertical blank with no DataEnable "DE" asserted.
I do not know what causes the interrupt not being served. I follow the vdma example that comed with Xilinx VDMA core, but the interrupt handler is never called.
I get the following status:
MM2S_DMASR=0x00200090 [DMAIntErr and SOFEarlyErr]
S2MM_DMASR=0x00030811 [SOFLateErr, DMAIntErr and halted]
Can anyone give me a tip to debug this case?
Thanks in advance
01-06-2014 10:47 AM
01-07-2014 11:30 PM
AFAIK, the timing controller is not a free IP. So I developed my own time and pattern generator.
The SOF on 1 side and free running on the other seems logic. I am confused between the usage of an FSYNC and the SOF, do they serve the same goal? Can the SOF on TUSER run the system without FSYNC?
I want the simplest solution to catch an incooming video stream to a DDR, and re-display it.
01-08-2014 04:44 AM
I managed to fix the interrupt serving, but still have the same status registers error.
The below image shows that the locked signal of the "v_axi4s_vid_out" gets high for a single line time, then down again. The peripheral does not forward any timing signals out. I checked with an oscilloscope, no timing signals are getting out of the FPGA.
How should I connect my generated SOF to the s2mm TUSER? The streaming interface is driven by "v_vid_in_axi4s".
Please check my updated mhs.
Thanks in advance,
01-08-2014 08:27 AM - edited 01-08-2014 08:29 AM
Sorry, this is a bit confusing in the older versions of this core. Set C_USE_FSYNC should be 3 (to put S2MM side in fsync mode and leave mm2s in free run mode). Then, you need to set the fsync_src bit in the s2mm control register to use SOF on TUSER as the fsync source.
When you enable fsync with C_USE_FSYNC, then it exposes the fsync port. At this point, you can use either the FSYNC pin or tuser as the 'frame sync' source. This is selectable at run-time on the control reg. They both serve the same purpose which is to indicate to the VDMA when to start transfers. Which one you select depends on your needs. In most cases, it is easiest to just use SOF on TUSER.
Also, make sure your axi stream to vid out core is in master mode.
01-09-2014 02:59 AM
I have applied your tips. Now the status changed to:
Write Channel: till has errors with status 0x00030811 I tried to clear all errors but they keep getting back and more errors count up. The last "1" means the channel is actually halted.
Read Channel: all errors vanished, it seems that running freely makes more frames per second ~25 fps, it was about 15 when FSYNC=1, although I have 60fps video IP source.
The problem is with the axis_video_out IP, it does not work, not even passing the timing signals out. I configured it to master as you pointed, but with no change.
Any tip is highly appretiated, I need to get the vdma working ASAP, please.
01-09-2014 06:40 AM
I fixed a firmware issue, now write channel works but at lower rate (~10fps), the write channel gets many errors:
EOLLate - SOFLate - EOLEarly - SOFEarly - DMAInt
Thos signals are generated from my IP, coded in VHDL, cannot be late!
Is there a preferred fifo size or buffer that can elliminate those errors?
Still not video out lock, nor timing signals come out.