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Newbie dvrosecpld
Newbie
52,068 Views
Registered: ‎10-29-2007

VHDL I2C Slave core

Does anyone have a stripped down I2C slave core that is open source?
 
The target device is a Spartan 3E FPGA in VHDL.
 
Thanks in advance.
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30 Replies
Newbie jgassel
Newbie
52,041 Views
Registered: ‎11-13-2007

Re: VHDL I2C Slave core

I would be interested in this too!  Anyone have something available?
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Highlighted
Instructor
Instructor
52,032 Views
Registered: ‎08-14-2007

Re: VHDL I2C Slave core

This is Verilog, not VHDL.  But it is a simple I2C slave controller.
It behaves like a small (256-byte max) EEPROM if you attach
it to a memory (distributed or block RAM).

I2C Addressing is 7-bit.

Tested with 100 KHz I2C and input clocks in range of 5 to 80 MHz.
Higher clock rates may work if the debouncing is made more
robust.  I2C pins are debounced/deglitched to deal with the
slow rise times compared to the clock rate.
Internal connections are simple 8-bit buses for subaddress, read data, and write data.
The original code was written in Abel, so the Verilog version does not
use obvious state machines.  However it is well annotated...
The module does not include the memory or registers, it only supplies
the register address and connects to external memory or registers.
For most designs I attach a small RAM to this module to provide
register readback and simplify the readback multiplexer.

There is no provision for clock stretching.  It is assumed that data
is always available when required from the FPGA internals.  This
is not usually a bad assumption.

Module Ports:
sda_io   - connect to the I2C SDA pin.
scl_in - connect to the I2C SCL pin (input only - no clock stretching).

rd_bus_7_0_in - connect to 8-bit wide readback mux or data output of RAM
clk_in - constant system clock.  5-80 MHz range has been tested.
clr_in - active high reset to module
subaddr_7_0_out - 8-bit subaddress for internal register selection or RAM address
wr_bus_7_0_out - 8-bit data for writing registers or RAM data input
wr_pulse_out - single cycle active high write enable to registers or RAM
rd_pulse_out - single cycle active high read pulse for read side-effects
rd_wr_out - Direction output for decoding read (high) or write (low) cycles

Regards,
Gabor

-- Gabor
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Newbie jukbys
Newbie
43,226 Views
Registered: ‎11-19-2009

Re: VHDL I2C Slave core

Hi Gabor,

 

I have a question.

Does this core work with input clock 1MHz for 400KHz transaction?

 

 

Best regards,

Junji

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Instructor
Instructor
43,225 Views
Registered: ‎08-14-2007

Re: VHDL I2C Slave core

I would suggest running the clock at least 8 times faster than the I2C bit rate.  This core

samples the SCL and SDA signals somthing like a UART where the clock is asynchronous

to the I2C data stream, so you need extra samples to be sure you catch all the transitions.

-- Gabor
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Contributor
Contributor
43,208 Views
Registered: ‎06-12-2009

Re: VHDL I2C Slave core

There is an I2C core in VHDL on www.opencores.org .... with a BSD license.... called "I2C Master Slave" .  The source for it is mostly a state machine as I would expect ... it looks fairly easy to work with.

Jim

 

 

 

 

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Newbie jukbys
Newbie
43,049 Views
Registered: ‎11-19-2009

Re: VHDL I2C Slave core

thank you very much
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Explorer
Explorer
43,024 Views
Registered: ‎02-18-2008

Re: VHDL I2C Slave core

Hi,

 

I'm working on a VHDL implememntation, but I have not finished...

 

I'm not sure it's good but for now I have tested with my FPGA (Spartan3e Starter kit) and an external circuit with pic18f4550

 

The vhdl code, receive 3 byte send from the pic...

 

The core is able to detect if the packet is for him and then receive, otherwise no.

 

I have also the testbench but now I add only the core...There are some features to implement

 

Any advice will be helpfull

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Explorer
Explorer
40,445 Views
Registered: ‎08-02-2007

Re: VHDL I2C Slave core

It looks like the core does support clock stretching. It just looks like Xilinx uses a different terminology in the data sheet to explain clock stretching.

From the IIC data sheet:

    Throttle Description

    The Philips I2C-bus Specification permits devices to throttle (suspend)
    data transmission on the bus by holding the SCL line low for an indefinite
    period of time.
    (DS606 December 2, 2009, page 24)
   

From the Philips spec:

    3.9 Clock stretching

    Clock stretching pauses a transaction by holding the SCL line LOW. The
    transaction cannot continue until the line is released HIGH again.
    (UM10204, I2C-bus specification and user manual, Rev. 03, 19 June 2007,
     http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf)

 

 

Hope this is helpful

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Newbie irfan449
Newbie
39,365 Views
Registered: ‎09-26-2010

Re: VHDL I2C Slave core

Hello Alex, I am Mohammed Irfan Working as Assistant professor, for one of my projects i am working on i2c interface. i was going through your i2c core,but unable to simulate it. can you please send your updated i2c core with testbench. my email id is irfan449@yahoo.com Thanks in Advance Irfan
Tags (1)
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Visitor 107444
Visitor
18,728 Views
Registered: ‎12-06-2010

Re: VHDL I2C Slave core

There is some exemple of I2C program ?

tanks!

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Newbie seemab
Newbie
18,406 Views
Registered: ‎05-18-2011

Re: VHDL I2C Slave core

Just wondering why it is names I2C slave? Do I need a master code too? New to VHDL, so wondering what I need to change/modify in the code to work on a Spartan 3E FPGA.


Thanks
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Teacher eteam00
Teacher
18,403 Views
Registered: ‎07-21-2009

Re: VHDL I2C Slave core

Just wondering why it is names I2C slave? Do I need a master code too?

I2C bus transactions are initiated by an I2C master.  The responding device is called the I2C slave.  The bus interface logic for a master is quite different from the slave bus interface logic.

 

Here is a useful article describing I2C.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Historian
Historian
18,394 Views
Registered: ‎02-25-2008

Re: VHDL I2C Slave core

 


@107444 wrote:

There is some exemple of I2C program ?

tanks!


Programs run on processors and computers. I have some example code that runs on a Silicon Labs 8051, if that would help.

 

----------------------------Yes, I do this for a living.
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18,292 Views
Registered: ‎06-21-2011

Re: VHDL I2C Slave core

I'd recommend this very simple and condensed fpga i2c core, the fpga used as a master to control peripheral i2c parts.

 

http://skytek.x10.mx

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Scholar vanmierlo
Scholar
18,052 Views
Registered: ‎06-10-2008

Re: VHDL I2C Slave core

To alexgiul,

 

I found your i2cSerialInterface.vhd here but it seems to be incomplete. The states data_written and stx_stop are (almost) empty and lock up the statemachine. Do you have an updated version?

 

Maarten

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Visitor mmc01
Visitor
17,877 Views
Registered: ‎09-23-2011

Re: VHDL I2C Slave core

Do you have an Example for using  "I2C Master Slave" from  www.opencores.org ? How to seperate that code and send data between Master and Slave?

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Teacher eteam00
Teacher
17,871 Views
Registered: ‎07-21-2009

Re: VHDL I2C Slave core

Do you have an Example for using  "I2C Master Slave" from  www.opencores.org ?

 

Most opencores projects include simulation testbenches.  What "Example" are you missing?

 

How to seperate that code and send data between Master and Slave?

 

I don't understand this question.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor omeryogev
Visitor
17,758 Views
Registered: ‎12-15-2011

Re: VHDL I2C Slave core

Hello,

I'm also looking for a simple I2c slave vhdl code. My final goal is to make a simple mux controlled by I2c.

I'm not looking for the massive http://opencores.org/ code that include a master logic and include a lot of LOC.

I'm looking for simple open soure code that can set a Slave I2C component for the Xilinx's XPS_I2C (Implamented in a Microblaze).

I was looking all over for a proper code in VHDL and I couldn't find one. Any ideas?

Tags (1)
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17,556 Views
Registered: ‎02-23-2012

Re: VHDL I2C Slave core

Hi All

 

I took the verilog version and converted it to VHDL. I have used this in a Lattice MACHXO connected to a 256byte EBR and it works a treat.

 

If anyone wants me to upload the VHDL source, let me know.

 

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Observer manojb.jgi
Observer
13,292 Views
Registered: ‎11-15-2011

Re: VHDL I2C Slave core

just attach it, we shall have a look, and make changes and use in our project

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13,161 Views
Registered: ‎07-22-2012

Re: VHDL I2C Slave core

 

can you please guide me how to use the "I2C master slave cor" in an fpga design to read and write data.?

 

 

regards,

saima

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Visitor pranavvhdl
Visitor
12,059 Views
Registered: ‎02-25-2014

Re: VHDL I2C Slave core

I just read the provious info and was very helpful thank you very much

 

Now im in a situation where i need to interface Xilinx FPGA to the EPROM the above code was helpful which is in VHDL but the code does not contain FSM and EPROM address interface done 

 

The other chalange here is creation of memory regisiters and calling it....... please provide a solution waiting for your valuble response 

 

"I am trying to do byte write and Random Read" 

 

It would be great if i need a code because i just need to interface as i am working on ARM board and these module is one which is in VHDL and i need to onterface this with the ARM board for some application.

 

Also provide any source code links, any writern code, FSM exact solutions anything is really a great help 

 

Waiting for you valuble response 

 

Thanks in advance 

P

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Visitor pranavvhdl
Visitor
12,056 Views
Registered: ‎02-25-2014

Re: VHDL I2C Slave core

alexgiul refereed your code and it was really helpful but if it is for EPROM it would be awesome
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Visitor pranavvhdl
Visitor
12,055 Views
Registered: ‎02-25-2014

Re: VHDL I2C Slave core

I just read the provious info and was very helpful thank you very much

Now im in a situation where i need to interface Xilinx FPGA to the EPROM the above code was helpful which is in VHDL but the code does not contain FSM and EPROM address interface done

The other chalange here is creation of memory regisiters and calling it....... please provide a solution waiting for your valuble response

"I am trying to do byte write and Random Read"

It would be great if i need a code because i just need to interface as i am working on ARM board and these module is one which is in VHDL and i need to onterface this with the ARM board for some application.

Also provide any source code links, any writern code, FSM exact solutions anything is really a great help

Waiting for you valuble response

Thanks in advance
P
Tags (2)
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Historian
Historian
12,044 Views
Registered: ‎02-25-2008

Re: VHDL I2C Slave core


@pranavvhdl wrote:
I just read the provious info and was very helpful thank you very much

Now im in a situation where i need to interface Xilinx FPGA to the EPROM the above code was helpful which is in VHDL but the code does not contain FSM and EPROM address interface done

The other chalange here is creation of memory regisiters and calling it....... please provide a solution waiting for your valuble response

"I am trying to do byte write and Random Read"

It would be great if i need a code because i just need to interface as i am working on ARM board and these module is one which is in VHDL and i need to onterface this with the ARM board for some application.

Also provide any source code links, any writern code, FSM exact solutions anything is really a great help

Waiting for you valuble response

Thanks in advance
P

You're asking us to do your work for you. That is not why this forum exists.

 

We can help with specific design issues, but to ask us to "provide a solution" is off topic. If you wish, you can engage in a consulting agreement with someone who can do the work for you.

----------------------------Yes, I do this for a living.
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Visitor pranavvhdl
Visitor
12,029 Views
Registered: ‎02-25-2014

Re: VHDL I2C Slave core

thanks for the quick response.... I Know how the forum works.... i am not asking anyone to do my work...... thats not the way things works....... there are some people who have worked i just need to share any examples to understand......... and i dont need the code or algo i just need any link or any information which can solve this problem........its as simple as that........
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Contributor
Contributor
6,653 Views
Registered: ‎02-05-2014

Re: VHDL I2C Slave core

Hi Julian

 

I am trying to interface I2C present on spartan6 fpga board, for that I have written vhdl code. But, while programming the bit file I not geting acknowledge from slave (i2c on borad). I am sending start signal then device address ("1010100")  but not getting ack from slave.

If you have completed i2c interface, please guide me what could be the reason.

 

Thanks in advance

Shiva

Shiva
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Xilinx Employee
Xilinx Employee
6,646 Views
Registered: ‎09-05-2007

Re: VHDL I2C Slave core

Check that your code defines the equivalent of 'open collector' on your I2C signals. 

 

There is an I2C reference design provided in the PicoBlaze (KCPSM6) package.

 

http://www.xilinx.com/ipcenter/processor_central/picoblaze/member/

 

The design is presented on the KC705 board but provided useful reference code (e.g. I/O definition in VHDL). Beyond the I2C signalling you then need to interact with the slave device and that's when PicoBlaze can be your controller in a very small footprint.

 

  

Ken Chapman
Principal Engineer, Xilinx UK
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Contributor
Contributor
6,636 Views
Registered: ‎02-05-2014

Re: VHDL I2C Slave core

Dear Sir

 

Thanks for your reply.

I was gone through the readme file and tried to add vdh file in ise to check on fpga board.

I have added first this "kc705_kcpsm6_i2c_eeprom" file, which has many component instatiations, out of all I am unable to find "m24c08_i2c_uart_bridge" this file to proceed.

Please suggest me, if I am going wrong.

 

By the way, I have downloaded the BIST design for Spartan6 SP605, and programmed the "download.bit" also "hello_iic.elf" file which proves that the I2C present on board is working fine.

 

But, still I am not getting ack from slave. There might be problem related to clock "scl" or something else which I am not getting. I have written code in vhdl on ise 14.7, and trying to interface with eeprom present on board.

 

Please suggest me few steps by which I can procedd.

 

 

Thanks and Regards 

Shiva
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