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Registered: ‎12-10-2009

Weird Block RAM behavior (Spartan 3A 200)

Hi All, 


Let's see if someone can give me a hand with this. It looks weird but I would like to know if somebody ever experienced something like this before. 



I have a design with a top level block and several  subblocks (20ish). It uses two DCMs and different FIFOs/Block RAM calls. 

The design itself works just fine and uses 12/16  RAMB16BWEs.


All of the sudden I add one output on a children block, dynamically assigned in a process within this children block and read it back on the top level. The signal I added is a std_logic_vector of 4 bits.

Well the problem is that now, only adding that signal, I get this error:


ERROR:Pack:2310 - Too many comps of type "RAMB16BWE" found to fit this device.
ERROR:Pack:18 - The design is too large for the given device and package.  Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. 


I check the RAMB16BWEs and Place&Route needs now 20/16 RAM blocks.


It does not make any sense because I did not add any RAM component in that single step. 


Let me guys know what I am doing wrong.


Target :  xc3s200a-4vq100

ISE :  Release 11.1/Application Version L.33





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Xilinx Employee
Xilinx Employee
Registered: ‎08-13-2007

Keep in mind that:

-BlockRAM can be implemented several ways (CoreGen or other netlist, direct instantiation, HDL inferrence, unimacro [newer families], etc.)

-synthesis and map can remove logic that hasn't been used


While it is possible you accidentally described a RAM with your new code (though I doubt it from your description), it is more likey that something was getting optimized out before that isn't now...


A few suggestions:

-diff the synthesis report file (.syr for XST, .srr for Synplify) before and after the change

-temporarily target a larger part and use FPGA Editor to look at the BRAM usage to determine what is going on

-you could also look at the Technology schematic view from synthesis but that may take longer for larger designs.





== edit. Also note that 11.4 is now available. I don't think that is the source of your problem, but there were many bug fixes integrated in 11.2 through 11.4

Message Edited by timpe on 12-10-2009 08:11 PM
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